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5results about How to "Avoid Fragmentation Risk" patented technology

Method for manufacturing wafer based on chemical etching method

The invention discloses a method for manufacturing a wafer based on a chemical corrosion method, and relates to the technical field of chips, in particular to the technical field of wafer manufacturing. According to the specific scheme, a wafer and a crystal ingot are separated through a corrosion method of an acid corrosion mixed solution, the separation process is milder, the fragment risk caused by ultrasonic vibration can be avoided, laser burning points can be evenly removed, meanwhile, the roughness of a separation face is reduced, the surface planarization is improved, and the surface quality is improved. And the processing time of the subsequent grinding procedure and the loss of the grinding wheel can be reduced. Besides, in the etching process of the acid corrosion mixed solution on the laser modified layer, part of hydrogen can be generated while the modified layer is dissolved, so that a mixed solution flowing channel is formed in the modified layer, the wettability of the mixed solution can be enhanced by adding the polyoxyethylene ether surfactant, flowing of the mixed solution is promoted, and the corrosion resistance of the laser modified layer is improved. And meanwhile, bubbles can be prevented from growing up to hinder contact between removed substances and mixed liquid, so that the ablation efficiency and uniformity of the laser ablation layer are improved.
Owner:INST OF LASER MFG HENAN ACAD OF SCI

Wafer box

The utility model provides a wafer box, which comprises a wafer bearing chamber, an air inlet cavity and an air outlet cavity, and is characterized in that the wafer bearing chamber comprises a plurality of bearing parts arranged at intervals, and each bearing part is provided with at least one adsorption air passage; the air inlet cavity is adjacent to the wafer bearing chamber, and a plurality of first air channels communicating the wafer bearing chamber with the air inlet cavity are arranged between the air inlet cavity and the wafer bearing chamber. The first air channels penetrate through the bearing part in the horizontal direction. The air outlet cavity is adjacent to the wafer bearing chamber, a plurality of second air channels communicating the wafer bearing chamber with the air outlet cavity are arranged between the air outlet cavity and the wafer bearing chamber, the first air channels penetrate through the bearing part in the horizontal direction, the adsorption air channels are opened from the surface, bearing wafers, of the bearing part, and the bottoms of the adsorption air channels are communicated with the first air channels and / or the second air channels; the first air channel and the second air channel are oppositely arranged in the horizontal direction, and the transverse section size of the adsorption air channel is smaller than the longitudinal section size of the first air channel and the longitudinal section size of the second air channel. According to the wafer box provided by the utility model, the cleanliness of the internal wafer is ensured, and the risk of fragmentation of the wafer in the cleaning process is avoided at the same time.
Owner:SIEN (QINGDAO) INTEGRATED CIRCUITS CO LTD

Wafer and processing thereof

This application relates to the field of integrated circuit manufacturing and discloses a wafer processing technology, including: obtaining a wafer after back cleaning; cleaning the back side of the wafer with an alkaline solution to neutralize the acidic substances remaining on the back side of the wafer after back cleaning; and performing photolithography on the wafer after cleaning with the alkaline solution. This application cleans the back side of the wafer with an alkaline solution before performing photolithography on the back side of the wafer after back cleaning. The alkaline solution can neutralize the acidic substances remaining on the back side after back cleaning. Because the acidic substances remaining after back cleaning are neutralized and removed, even if there are chemical residues at the edge of the back side after photolithography, white crystal defects will not be generated at the edge of the back side of the wafer, improving wafer quality and avoiding the risk of subsequent wafer breakage. Furthermore, this application also provides a wafer with the above advantages.
Owner:SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO LTD

De-bonding method and de-bonding device

The invention relates to a de-bonding method and a de-bonding device. The de-bonding method comprises the following steps that a bonding structure is formed, the bonding structure comprises a wafer and a slide glass, the wafer comprises a bonding surface and a back surface which are oppositely distributed, the bonding surface of the wafer is in bonding connection with the slide glass, and a metal layer is formed on the back surface of the wafer; placing the bonding structure onto a bottom chuck in a processing chamber in a direction in which the slide glass faces the bottom chuck; and adsorbing and thermally slipping the wafer above the bottom chuck, and separating the wafer from the slide glass. According to the invention, the metal layer on the back surface of the wafer can be prevented from being oxidized in the de-bonding process, so that the de-bonded wafer can be directly scribed or delivered, and the risk of fragmentation caused by deposition of the metal layer on the back surface after de-bonding is avoided.
Owner:GTA SEMICON CO LTD

Power semiconductor devices and their manufacturing processes

ActiveCN112397380BAvoid Fragmentation Risklow costSemiconductor devices
The present application relates to the technical field of power semiconductor devices, and more specifically, to a power semiconductor device and its manufacturing process. The manufacturing process of the power semiconductor device includes the following steps: depositing an epitaxial layer on the front side of the substrate and completing the manufacturing of the front structure of the power semiconductor device; etching the back side of the substrate, etching through the entire substrate until the epitaxial layer, and forming a lead hole; filling the lead hole with metal and accumulating it on the back side of the substrate to form a back metal layer, and annealing the alloy, connecting the epitaxial layer to the back metal layer through metal leads. This process does not require thinning the substrate, but uses lead hole technology to lead out the back electrode. On the basis of not affecting the welding process and the electrical properties of the power semiconductor device, the thinning process is abolished, and the substrate is retained as a support, avoiding the risk of fragmentation caused by the thinning process and the subsequent thin film manufacturing process, and saving costs.
Owner:GREE ELECTRIC APPLIANCE INC OF ZHUHAI