32results about How to "Avoid Fragmentation Risk" patented technology

The invention discloses a thin wafer de-bonding method, which comprises the following steps of: 1, removing silicon etching on the outer ring of a silicon wafer undergone glue denaturation or glue overflow; and 2, de-bonding the silicon wafer and slide glass. A etching removal method in the first step comprises the steps of: preparing a mask layer on the wafer side, the mask layer is made of positive or negative photoresist, and the photoresist on the edge of the silicon wafer is removed through an exposure and development process; and directly etching the outer ring of the silicon wafer through a dry etching process. Aiming at the problems of thin wafer temporary bonding glue denaturation and glue extrusion, a de-bonding pretreatment method is adopted, silicon etching on the outer ring ofthe silicon wafer undergone glue denaturation or glue overflow is removed through mask preparation, etching and edge removal and other pretreatment processes, and then the de-bonding process is carried out, so that the problem that de-bonding cannot be smoothly carried out due to temporary bonding glue denaturation is solved, and the risk of fragmentation is avoided.

The invention discloses a substrate carrier platform and an exposure machine. The substrate carrier platform comprises a body and at least one first electrostatic eliminator, wherein the body comprises a first surface and a second surface which are arranged opposite to each other; the first surface is used for carrying a substrate and is provided with at least one ion channel; each first electrostatic eliminator corresponds to at least one ion channel; the first electrostatic eliminators are respectively connected with the corresponding ion channels so as to provide electrostatic elimination ions for the ion channels. By means of the action of the ion channels and the first electrostatic eliminators corresponding to the ion channels, the static electricity generated by the surface, in contact with the substrate carrier platform, of the substrate can be eliminated, so that the electrostatic absorption force between the substrate and the substrate carrier platform can be eliminated, andthe substrate and the substrate carrier platform can be easily peeled off. Therefore, in a process of peeling off the substrate from the substrate carrier platform, the substrate can be effectively protected, the risk of breaking is effectively avoided when the substrate is peeled off, the production yield of the substrate is increased, and the manufacturing cost is reduced.

The invention provides a monitoring method, attachment equipment and a panel. By the monitoring method, the attachment equipment and the panel, a breakage risk caused by that stress applied onto a glass substrate is not within an error-allowable range during the fabrication process of an OLED display panel is reduced. The monitoring method comprises the steps of detecting pressure values of a plurality of points by a piezoelectric sensing thin film arranged between a lamination plate and a substrate; determining whether the stress applied to the substrate by the lamination plate is within theerror-allowable range or not according to the pressure values of the plurality of points; and controlling running of the lamination plate according to the situation whether the pressure is within theerror-allowable range or not so that the substrate is uniformly pressed on a mask.

The invention provides a semiconductor device manufacturing method, a semiconductor device and an electronic device; the method comprises the following steps that a semiconductor substrate is provided, wherein a terminal ring region and a cell region are formed on the semiconductor substrate; and a protective layer for covering the terminal ring region and a supporting structure positioned on thecell region are formed on the semiconductor substrate, wherein the top of the supporting structure is lower than the top of the protective layer or is flush with the top of the protective layer. According to the manufacturing method of the semiconductor device, the semiconductor device and the electronic device, the supporting structure located in the cell region is formed on the semiconductor substrate, so that the height difference between the top of the cell region structure and the top of the structure of the terminal ring region is reduced before the back surface of a wafer is thinned, afilm stripping process and fragment risk due to the film stripping process caused by using an organic protective film as a buffer layer in the subsequent grinding thinning process can be avoided, theprocess flow is simplified, and meanwhile, the generation of fragments or micro-cracks is reduced.

The invention provides a liquid crystal panel packaging box, which includes a box cover and a box body, at least one counting insert and a plurality of quadrangular spacers are arranged inside the box body, and at least one groove is arranged on the inner wall of the box body , the counting insert is fixed in the groove; the four corners inside the box are rounded, and at least two corners of each spacer are provided with circular lugs, and the circular lugs are fixed within the corresponding rounded corners of the box. The present invention facilitates packing and counting of the liquid crystal panel by adding a number plug-in on the side wall of the box body; by setting a circular lug structure on the spacer and fixing it on the corner of the box body, it is convenient to fix the spacer when the liquid crystal panel is boxed , and thus effectively prevent the risk of fragmentation that may occur due to the failure of the limit during the packing and transportation of the LCD panel.

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a substrate front surface and a substrate back surface, and the substrate front surface and the substrate back surface are each sequentially provided with a dielectric layer and a bonding layer in a stacked manner; an isolation structure is formed on the front face of the substrate, the isolation structure penetrates through the attaching layer and the dielectric layer and extends into the substrate, and the isolation structure covers the surface of the attaching layer; forming buffer layers on the surfaces of the isolation structures and the surfaces of the bonding layers on the back surface of the substrate; removing the buffer layer, the bonding layer and the isolation structure higher than the dielectric layer on the front surface of the substrate; forming gate material layers on the surfaces of the dielectric layer and the isolation structure on the front surface of the substrate and the surface of the buffer layer on the back surface of the substrate; and taking the buffer layer and the gate material layer on the back surface of the substrate as protective layers, and executing subsequent processes in the logic device region. According to the technical scheme, the bonding layer can be protected from being damaged, the integrity of the bonding layer is ensured, and the performance and the yield of the logic wafer are improved.

The invention provides a back metallized semiconductor structure and a preparation method thereof, and the preparation method of the back metallized semiconductor structure comprises the following steps: providing a substrate with a first surface and a second surface which are oppositely arranged, and forming a semiconductor device at one side, close to the first surface, of the substrate; forminga groove for communicating the second surface with the semiconductor device in the substrate; and forming a back metal layer on the second surface and the surface of the groove. According to the invention, the groove and the back metal layer are formed on the back surface of the wafer, so that the original back thinning and metallization process is replaced, the fragment risk caused by back thinning is avoided, the product yield is further improved, and the product production cost is reduced.

The invention discloses a substrate carrier and an exposure machine. The substrate carrier includes: a body, including a first surface and a second surface oppositely arranged, the first surface is used to carry the substrate, and the first surface is provided with at least one ion channel; at least one first static eliminator, each first The static eliminator corresponds to at least one ion channel, and the first static eliminator is connected to the corresponding ion channel to provide static elimination ions into the ion channel. Through the function of the set ion channel and the first static eliminator corresponding to the ion channel, the static electricity generated on the surface in contact with the substrate and the substrate carrier can be eliminated, thereby eliminating the electrostatic adsorption force between the substrate and the substrate carrier , so that the substrate and the substrate carrier can be easily peeled off. Therefore, in the process of peeling the substrate from the substrate carrier, the substrate can be effectively protected, the risk of debris during the peeling of the substrate can be effectively avoided, the production yield of the substrate can be improved, and the production cost can be reduced.

The present invention relates to the technical field of OLED packaging, and in particular to a substrate arrangement and buffer device, which is used to store abnormal substrates by setting the arrangement and buffer device, and cooperates with the processor by setting the extraction device to detect the glue coating device and the pressing pair. When there is an abnormality in the substrate in the assembly device and the frame glue curing device, the horizontal turntable is controlled to rotate to the corresponding position, and the manipulator is driven to take out the abnormal substrate and put it into the buffering device, which avoids the risk of fragmentation during the OLED packaging process, thereby improving OLED. Panel production efficiency and ensure the continuity of production.

The present utility model provides a crystal boat converter which comprises a pedestal, the pedestal is provided with a bearing plate, a first positioning area and a second positioning area are further formed along the first direction on the bearing plate, and a first blocking device is arranged on the bearing plate, specifically on the outer edge of one end of the second positioning area, which is far away from an spacing part. The height of the first blocking device is larger than the width of the spacing part, a blocking surface is formed by the first blocking device, and the blocking surface is faced with the spacing part. The second positioning area also comprises a second blocking device which is protruded on the bearing plate, thus operating personnel can be ensured by the first and second blocking devices to displace or fetch the crystal boat in a correct direction, thus the safety of wafers can be increased.

The invention discloses a manufacturing process control system and an analysis method, which belong to the technical field of semiconductor manufacturing process management and control. The semiconductor manufacturing process control system comprises an acquisition unit, a first storage unit, a processing unit and an alarm unit, wherein the acquisition unit acquires wafer original data; the first storage unit stores the wafer original data; the processing unit extracts the wafer original data and processes the wafer original data to obtain multiple groups of grouped data, and analyzes and outputs a variation trend of the grouped data; and the alarm unit receives an analysis result and outputs an alarm signal. The analysis method comprises the steps of: acquiring the wafer original data and storing the wafer original data in the first storage unit; extracting the wafer original data from the first storage unit, and processing the wafer original data to obtain the corresponding grouped data and dividing the grouped data into groups; and analyzing the variation trend of the grouped data, and outputting the analysis result to the alarm unit for alarm. The semiconductor manufacturing process control system and the analysis method have the beneficial effects of reducing alarm time delay and omission, avoiding fragment risk of products, and ensuring product yield.

The present invention provides a method for manufacturing a semiconductor device, a semiconductor device and an electronic device. The method includes: providing a semiconductor substrate on which a terminal ring region and a cell region are formed; A protective layer covering the terminal ring area and a support structure located on the cell area are formed on the top, wherein the top of the support structure is lower than the top of the protective layer or is flush with the top of the protective layer. According to the manufacturing method of the semiconductor device, the semiconductor device and the electronic device of the present invention, the support structure located in the cell region is formed on the semiconductor substrate, which reduces the gap between the top of the cell region structure and the top of the terminal ring region structure before the back of the wafer is thinned. The height difference avoids the risk of debris caused by the peeling process and the peeling process caused by using the organic protective film as a buffer layer in the subsequent grinding and thinning process, and reduces the occurrence of debris or microcracks while simplifying the process.

The invention provides a method of laser polishing glass and the polishing method of glass holes and glass sheets.Including the following steps: After the first laser is used to expose the cutting contour set on the glass plate, the glass is disconnected along the cut contour line; the second laser edge near the cut contour line of 0.3‑1.2mm to illuminate,Make the glass on both sides of the polishing contour evaporation and get polished glass products; the second laser is CO 2 Continuous laser.The present invention can solve the slight cracks and defects caused by the cut surface caused by conventional cutting methods; 2 Continuous laser directly illuminate the polishing contour line, so that the vitreous body evaporation and removal of the polishing contour lines on both sides of the outline, obtain a smooth glass side broken surface to improve the performance of glass mechanics;The quality of the plane solves the potential risk of subsequent processes.

A method for unbonding thin wafers, comprising the following steps: Step 1, etching and removing the silicon where the outer ring of the silicon wafer undergoes glue denaturation or glue overflow; and Step 2, unbonding the silicon wafer and the carrier. The etching removal method described in step 1 includes preparing a mask layer on the side of the wafer. The material of the mask layer is positive or negative photoresist, and the photoresist at the edge of the silicon wafer is removed through the exposure and development process. ; and then directly etch the outer ring of the silicon wafer through a dry etching process. Aiming at the problems of temporary bonding glue degeneration and "glue extrusion" of thin wafers, the present invention adopts a pre-treatment method for de-bonding, through pre-treatment processes such as mask preparation, etching and edge removal, etc. The silicon etching and removal of the glue overflow, and then the debonding process, solves the problem that the debonding cannot be carried out smoothly due to the denaturation of the temporary bonding glue, and avoids the risk of debris.

The invention discloses an interconnection test fixture and an interconnection test method for a silicon-based component, and belongs to the technical field of advanced electronic packaging, the interconnection test fixture for the silicon-based component comprises a vacuum adsorption hole, an X-axis limiting baffle block, a Y-axis limiting baffle block and a test area Z plane regulator, and realizes three-dimensional regulation of a tested piece. The problems of clamping and compatibility of different silicon-based assemblies are solved, the fragment risk is avoided, and the purposes that the test fixture is universal and convenient to use are achieved; according to the interconnection test method, direct current and alternating current characteristic tests are carried out by using an isolation technology, and test errors are reduced by reducing generated current branches, so that the accuracy of a measured value is ensured; according to the invention, the testing of the microsystem component level is realized, most of the fault components can be detected before the function performance test, the final function performance test first pass yield is improved, the subsequent potential quality hazard and resource waste are avoided, and the test coverage rate of the network is effectively improved.