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Wafer multilayer stacking bonding method

A multi-layer stacking and wafer technology, applied in the manufacturing of electrical components, electric solid-state devices, semiconductor/solid-state devices, etc., can solve problems such as wafer fragments, avoid splits, have broad application prospects and market potential, and improve assembly efficiency Effect

Pending Publication Date: 2022-02-15
XIAN MICROELECTRONICS TECH INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to overcome the disadvantages of the above-mentioned prior art that the use of temporary bonding materials to bond the wafer to the carrier easily leads to wafer fragmentation, and to provide a multi-layer stacking and bonding method of wafers and a multi-layer wafer structure

Method used

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Embodiment 1

[0040] In this embodiment, the used wafer is a 4M asynchronous SRAM (static memory) wafer, which is finally a 3-layer SRAM wafer bonding product, such as Figure 5 shown. The 3-layer SRAM wafer bonding method includes the following steps: the process is as follows Figure 7 as shown,

[0041] Step 1. The first layer of wafer is only re-wiring and bump preparation on the front side, lead out the pad, and the front side is re-wiring to 3 layers, and the bump is electroplated SnAg, with a height of 3 μm;

[0042] The second layer wafer and the third layer wafer first complete the front rewiring and bump preparation, the number of rewiring layers is 3 layers, the front bump is electroplated Cu, and the height is 5 μm;

[0043] Step 2. The SnAg bumps on the front of the first layer of wafer are metal-bonded with the Cu bumps on the front of the second layer of wafer. The bonding temperature is 260°C, the time is 30 minutes, the bump opening ratio is 1.5%, and the bonding pressure...

Embodiment 2

[0052] Except the following content, all the other content are the same as embodiment 1.

[0053] The TSV diameter is 5 μm and the depth is 50 μm;

[0054] The bonding temperature is 240°C, the bonding time is 60min, the bump opening ratio is 3.5%, and the bonding pressure is 6000N;

[0055] The front rewiring layer is 2 layers, and the rear rewiring layer is 4 layers.

[0056] In step 5, in the metallization layer on the back of the second wafer, the adhesion layer is 0.5 μm Ti, the barrier layer is 1 μm Cu, and the wetting layer is 2 μm Ni;

[0057] In step 8, in the metallization layer on the back of the third wafer, the adhesion layer is 0.1 μm Ti, the barrier layer is 2 μm Cu, and the wetting layer is 5 μm Cu;

Embodiment 3

[0059] In this embodiment, the used wafer is a 4M asynchronous SRAM (static memory) wafer, and finally is a 5-layer SRAM wafer bonding product, such as Figure 6 As shown, the preparation process is as follows Figure 7 shown.

[0060] Step 1. The first layer of wafer is only re-wiring and bump preparation on the front side, lead out the pad, and the front side is re-wiring to 2 layers, and the bump is electroplated Cu, with a height of 3 μm;

[0061] The second layer wafer and the third layer wafer first complete the front rewiring and bump preparation, the number of rewiring layers is 3 layers, the front bump is electroplated Cu, and the height is 5 μm;

[0062] Step 2. The Cu bumps on the front side of the first layer wafer are metal-bonded with the Cu bumps on the front side of the second layer wafer. The bonding temperature is 400°C, the bonding time is 90 minutes, the bump opening ratio is 2%, and the bonding pressure is 20kN; through the Cu-Cu metal bonding process, t...

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Abstract

The invention discloses a multilayer stacking bonding method for wafers, and belongs to the technical field of semiconductor integrated packaging. The bonding sequence is as follows: first layer, second layer wafer front process; first layer, second layer wafer bonding; one side wafer thinning and backside process; other side wafer thinning and backside process; third layer wafer front process and second and third layer wafer bonding ; and third layer wafer thinning and backside process, and a solution is provided for multilayer bonding of the thin wafer. According to the method, bonding of multiple layers of wafers can be carried out without additionally adding a slide glass, the number of layers of the bonded wafers is increased layer by layer according to the mutual bearing effect of the bonded wafers, and the risk that the wafers are cracked due to the fact that temporary bonding glue is denatured and difficult to unbond is avoided. Besides, compared with single-chip stacking, the method has the advantages that the assembling efficiency is remarkably improved, the method is an efficient multi-layer wafer level homogeneous or heterogeneous high-density integration method, the application prospect and market potential are very wide, and important strategic significance and social benefits are achieved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated packaging, and relates to a multilayer stacking and bonding method of wafers. Background technique [0002] At present, whether it is 2.5D TSV silicon interposer substrate integration or 3D TSV stacking of memory chips, the single-chip stacking process is used, and the assembly efficiency is low. Wafer bonding is a type of wafer-level chip-scale packaging (WLCSP), which is to package and test the entire wafer and then cut it into a single IC chip. The use of wafer-level bonding process in 3D stacking of memory chips or 2.5D TSV silicon interposer substrate integration will effectively improve assembly efficiency. However, TSV silicon interposer substrates or storage wafers that can often be bonded at the wafer level are thin wafers, which are fragile and flexible. Therefore, temporary bonding materials are usually used to bond the wafers during operation. onto the carrier. Wafe...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L21/603H01L21/768H01L25/065
CPCH01L21/50H01L24/81H01L21/76898H01L25/0657H01L2224/81201H01L2224/818
Inventor 张宁吴道伟霍瑞霞
Owner XIAN MICROELECTRONICS TECH INST
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