Interconnection test fixture and interconnection test method for silicon-based component

A test method and test fixture technology, which is applied in the direction of single semiconductor device testing, measuring device casing, etc., can solve the problems of no test fixture and test method, long production and debugging cycle, low test coverage, etc., to achieve application prospects and market potential Wide, improve the test pass rate, take into account the effect of efficiency and adequacy

Pending Publication Date: 2022-04-29
珠海天成先进半导体科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The former cannot check invisible welding defects, component failures, etc., and the test coverage is low; the latter needs to make test fixtures for different products, and the production and debugging cycle is long and the cost is high
Due to the characteristics of silicon-based components such as diversification, thinness, miniaturization, and high-density I / O contacts, there is currently no effective test fixture and test method for the interconnection test of silicon-based components.

Method used

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  • Interconnection test fixture and interconnection test method for silicon-based component
  • Interconnection test fixture and interconnection test method for silicon-based component
  • Interconnection test fixture and interconnection test method for silicon-based component

Examples

Experimental program
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Effect test

Embodiment

[0070] Taking the assembly test of a package on package and PoP of silicon-based components as an example, the interconnection test of silicon-based components is carried out from the aspects of DUT information, test process, test technology, test coverage and test time. illustrate.

[0071] DUT information

[0072] The DUT is a 3-layer silicon-based component PoP information processing micromodule, such as Figure 9 As shown, the uppermost layer is a silicon adapter board flip-chip 1 PowerPC processor die, the middle layer is a silicon adapter board flip-chip 3 DDR memory bare cores, and the bottom layer is a silicon adapter board flip-chip 2 Flash memory bare cores. core.

[0073] Table 1 DUT information

[0074]

[0075] It can be seen that the test surface requirements of PowerPC, DDR, Flash single-layer silicon-based components and DDR+Flash silicon-based components after 2-layer stacking are rear, double-sided, double-sided, and double-sided respectively; the heigh...

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PUM

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Abstract

The invention discloses an interconnection test fixture and an interconnection test method for a silicon-based component, and belongs to the technical field of advanced electronic packaging, the interconnection test fixture for the silicon-based component comprises a vacuum adsorption hole, an X-axis limiting baffle block, a Y-axis limiting baffle block and a test area Z plane regulator, and realizes three-dimensional regulation of a tested piece. The problems of clamping and compatibility of different silicon-based assemblies are solved, the fragment risk is avoided, and the purposes that the test fixture is universal and convenient to use are achieved; according to the interconnection test method, direct current and alternating current characteristic tests are carried out by using an isolation technology, and test errors are reduced by reducing generated current branches, so that the accuracy of a measured value is ensured; according to the invention, the testing of the microsystem component level is realized, most of the fault components can be detected before the function performance test, the final function performance test first pass yield is improved, the subsequent potential quality hazard and resource waste are avoided, and the test coverage rate of the network is effectively improved.

Description

technical field [0001] The invention belongs to the technical field of advanced electronic packaging, and in particular relates to an interconnection test fixture and an interconnection test method of a silicon-based component, which can be used for assembly defect detection in the development process of the silicon-based component. Background technique [0002] In recent years, the development of advanced packaging technology has shown the following trends: ① development from single chip to multi-chip; ② transformation from two-dimensional or 2D to three-dimensional or 3D; ③ heterogeneous and heterogeneous integration. 2.5D packaging can achieve high-density interconnection between multiple chips and packaging substrates through silicon interposers, and 3D packaging can achieve chip-to-chip bonding processes through chip-to-chip / chip-to-wafer / wafer-to-wafer bonding processes. Three-dimensional stacking of chips. Flip Chip, FC, or silicon-based components encapsulated by si...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/26G01R1/04
CPCG01R31/2601G01R1/0425
Inventor 潘鹏辉吴道伟姚华唐磊薛宇航
Owner 珠海天成先进半导体科技有限公司
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