Manufacturing method of semiconductor device, semiconductor device and electronic device

Abstract

The present invention provides a method for manufacturing a semiconductor device, a semiconductor device and an electronic device. The method includes: providing a semiconductor substrate on which a terminal ring region and a cell region are formed; A protective layer covering the terminal ring area and a support structure located on the cell area are formed on the top, wherein the top of the support structure is lower than the top of the protective layer or is flush with the top of the protective layer. According to the manufacturing method of the semiconductor device, the semiconductor device and the electronic device of the present invention, the support structure located in the cell region is formed on the semiconductor substrate, which reduces the gap between the top of the cell region structure and the top of the terminal ring region structure before the back of the wafer is thinned. The height difference avoids the risk of debris caused by the peeling process and the peeling process caused by using the organic protective film as a buffer layer in the subsequent grinding and thinning process, and reduces the occurrence of debris or microcracks while simplifying the process.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a semiconductor device, a semiconductor device and an electronic device. Background technique [0002] Insulated-gate bipolar transistor (IGBT) has become one of the most important high-power mainstream devices in the field of power electronics. As a high-power discrete device, reducing static (Vcesat) and dynamic (Eoff) power consumption has always been the development direction of IGBT. Theoretically, static (Vcesat) and dynamic (Eoff) power consumption are mutually restricted (trade-off). [0003] In the existing IGBT structure, by further thinning the device thickness, simultaneous optimization of static (Vcesat) and dynamic (Eoff) power consumption can be achieved. This is also the development direction of the new generation IGBT of the international mainstream IGBT manufacturers. However, as the thickness of the device decreases, great...

AI Technical Summary

Problems solved by technology

However, as the thickness of the device becomes thinner, it brings great challenges to the grinding process and the subsequent laser annealing (LTA) process

[0004] A typical IGBT structure includes a terminal ring area and a cell area (cell), wherein, on the front of the IGBT, due to the presence of a terminal ring structure in the terminal ring area and a protective layer covering the terminal ring area, such as a polyimide (polyimide) film layer, Causes a height difference between the terminal ring area and the cell area on the front side, which often leads to chips or microcracks in the back grinding thinning process

Debris leads to device failure, and microcracks also cause wafer fragmentation in the subsequent laser annealing process

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