Semiconductor device and method for manufacturing the same

Abstract

A method and structure directed to providing a source/drain isolation structure. The method includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of anILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region. Embodiments also relate to a semiconductor device anda method for manufacturing the same.

Description

technical field [0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background technique [0002] The electronics industry has a growing demand for smaller and faster electronic devices capable of supporting a greater number of increasingly complex and sophisticated functions at the same time. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low cost, high performance and low power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down semiconductor IC dimensions (eg, minimum feature size) and thereby increasing production efficiency and reducing associated costs. However, this scaling down has also increased the complexity of the semiconductor manufacturing process. Accordingly, achieving continued advances in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies. [0003] In particul...

AI Technical Summary

Problems solved by technology

However, during at least some conventional processes, the sharply scaled-down cut metal regions used to at least partially define the dimensions of the dielectric layer result in the dielectric layer not providing sufficient isolation

In some instances, and due to the scaled down cut metal area, bridging (e.g., electrical shorting) may occur between the metal contact layer and adjacent source / drain features

In addition, the dielectric layer of the isolated area may suffer from time-dependent dielectric breakdown (TDDB), and thus cannot provide the required isolation

In some cases, the hardmask used to keep adjacent metal contact layers apart may lift off during processing (eg, during etching to provide a patterned dielectric layer for isolation regions), resulting in Electrical short between subsequently formed adjacent metal contact layers

Also, the materials used for the dielectric layer may themselves be more prone to poor reliability (eg, such as due to TDDB)

[0004] Therefore, the prior art has not proven to be fully satisfactory in all respects

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