cnn accelerator and electronics

Abstract

The present invention provides a kind of CNN accelerator and electronic equipment, and described CNN accelerator comprises the CNN trainer that is arranged in MCU kernel, the CNN engine that is arranged in FPGA kernel and CNN memory, can combine the data processing capability of MCU kernel and FPGA The combination of the parallel processing capability and programmability of the core improves the data processing speed and parallel processing capability of the CNN accelerator, and is compatible with the training and inference stages of the convolutional neural network. Moreover, the training weight value obtained by the CNN trainer is directly transmitted to the CNN engine, which can optimize the weight distribution between the layers in the CNN engine at any time, and reduce the inference error rate. In addition, using the storage resources of the FPGA core as the CNN memory saves the read and write time between each execution unit in the CNN engine and the CNN memory, and ensures the data read and write rate under a certain storage capacity, thereby speeding up the CNN accelerator. overall operational efficiency.

Description

technical field [0001] The invention relates to the technical field of convolutional neural networks, in particular to a CNN accelerator and electronic equipment. Background technique [0002] Artificial intelligence system (AI) is the study of the laws of human intelligence activities, the construction of artificial systems with certain intelligence, and the study of how to make computers complete the tasks that required human intelligence in the past, that is, to study how to use computer software and hardware to simulate human beings. Basic theories, methods, and techniques of certain intelligent behaviors. [0003] A convolutional neural network (CNN) is very similar to a normal neural network, consisting of neurons with learnable weights and bias constants. Each neuron takes some input and does some convolution and the output is a score for each class. The difference is that the default input of the convolutional neural network is an image, which allows us to encode s...

AI Technical Summary

Problems solved by technology

[0004] Most of the existing CNN accelerators are only implemented with a single core of a field programmable gate array (FPGA core), which is limited by the processing power (computing and storage), power consumption, cost, and volume of the FPGA core chip itself. Computing and storage complexity to meet the capabilities of the FPGA core chip itself, and usually only the inference stage of the convolutional neural network is implemented. The hierarchical structure of the engine inside the CNN accelerator and the weight distribution between layers are determined, which needs to be determined in advance. Completing the training process of the network is inflexible. Each layer of the engine must read and write data with the storage unit, which not only wastes memory resources, but also requires time and cost for each data read and write.

Images