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Semiconductor chip with hybrid wire bonding pad

A bonding pad and wire bonding technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve reliability problems, bonding wires fall off, affect bonding integrity, etc. question

Active Publication Date: 2021-01-05
INNOGRIT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Overlapping bonding and probing areas can cause reliability issues as the wires will be bonded on top of the probing area, which can affect bond integrity and cause bond wire lift issues
Therefore, there is space (or "real estate") contention in the pad design

Method used

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  • Semiconductor chip with hybrid wire bonding pad
  • Semiconductor chip with hybrid wire bonding pad
  • Semiconductor chip with hybrid wire bonding pad

Examples

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Embodiment Construction

[0011] Specific embodiments according to the present application will now be described in detail with reference to the accompanying drawings. For consistency, the same elements in the various figures are denoted by the same reference numerals.

[0012] Exemplary embodiments according to the present disclosure may provide a semiconductor chip which may include hybrid wire bonding pads. According to various aspects of the present disclosure, provided techniques can form at least two types of bonding pads on a semiconductor chip: external bonding pads extending in a first direction parallel to the edge of the semiconductor chip and external bonding pads extending in a first direction perpendicular to the edge of the semiconductor chip. Inner bonding pads extending in the second direction of the edge of the chip. The outer bond pad may have a probing area and two wire bonding areas arranged along a first direction, while the inner bonding pad may have a probing area and a wire bo...

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PUM

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Abstract

Apparatus and methods are provided for bond pad layouts and structures for semiconductor chips. According to various aspects of the present disclosure, provided techniques may provide a semiconductorchip that may include an outer bonding pad extending in a first direction parallel to an edge of the semiconductor chip and an inner bonding pad extending in a second direction perpendicular to the edge of the semiconductor chip. The outer bonding pad may have one probe region and two wire bonding regions aligned in a first direction, while the inner bonding pad may have one probe region and one wire bonding region aligned in a second direction. The outer bonding pad can be placed closer to the edge of the semiconductor chip than the inner bonding pad.

Description

technical field [0001] The present disclosure relates to semiconductor chips, and more particularly to wire bonding pads for semiconductor chips. Background technique [0002] Integrated circuits (ICs) are the fundamental building blocks of modern electronics. More and more functions are integrated into IC chips, and semiconductor chips need to provide more connections. Typically, connections are provided by wire bonding, which uses Au, Cu, Ag alloys, or any conductive wires to electrically connect the chip to the substrate or lead frame. The connection between the chip and the substrate allows input / output (I / O) signals on the chip to be input or output through pads located on the edge of the chip. In addition, the bond pad provides power and ground to the chip. In addition, the semiconductor chip needs to be tested before wire bonding, so it is also necessary to provide a test probe area through the bonding pad. Usually, the bonding pad is designed as a long pad separa...

Claims

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Application Information

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IPC IPC(8): H01L23/488H01L21/60
CPCH01L24/06H01L24/03H01L2224/04042H01L2224/0603H01L2224/06131H01L2224/06515H01L2224/039H01L22/32H01L24/05H01L2224/06165H01L2224/06155H01L2224/061H01L2224/05553H01L2224/4911H01L2224/05624H01L2224/05647H01L2224/48225H01L2224/48245H01L24/48H01L24/49H01L2924/00014H01L2224/06177
Inventor 不公告发明人
Owner INNOGRIT TECH CO LTD
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