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Stacked memory and ASIC device

A technology for memory chips and memory arrays, which is applied in the manufacture of electrical solid-state devices, semiconductor devices, and semiconductor/solid-state devices, and can solve problems such as high power consumption and limited memory bandwidth.

Pending Publication Date: 2021-01-05
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, memory bandwidth can be limited and laterally extending conductors can create additional parasitic RC delays and higher power consumption during bitline or wordline set operations

Method used

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  • Stacked memory and ASIC device
  • Stacked memory and ASIC device
  • Stacked memory and ASIC device

Examples

Experimental program
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Embodiment Construction

[0090] The following description is presented to enable one skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0091] figure 1 is a symbolic diagram of a memory wafer 110 on which several memory circuits have been fabricated, and an ASIC wafer 112 on which sense amplifiers and other bias voltage generators and support circuits for the memory circuits have been fabricated. on the ASIC wafer 112. ASIC wafer 112 may also include other advanced CMOS devices such as processor...

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PUM

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Abstract

The invention relates to a device including a memory chip having a memory array, bit lines in communication with data carrying nodes of the memory array, and word lines in communication with certain gate control nodes of the memory array. The memory chip has bonding pads formed on an interconnect surface at respective memory chip interconnect locations. Each of the bit lines and each of the word lines of the memory array includes a respective landing pad in a conductive layer of the chip, and these landing pads connected via redistribution conductors to respective ones of the set of memory chip bonding pads. The redistribution conductors for the bit lines have a positive average lateral signal travel distance which is less than that of the redistribution conductors for the word lines.

Description

technical field [0001] The present invention relates to an integrated circuit memory device. Background technique [0002] In the fabrication of high density memory devices, the amount of data per unit area on an integrated circuit can be a critical factor. Therefore, as the critical dimensions of memory devices approach the technology limit, multiple levels techniques for stacking memory cells have been proposed in order to achieve greater storage density per bit and lower cost. In addition, new memory technologies are being deployed, including phase-change memory, ferromagnetic memory, metal-oxide-based memory, and more. [0003] The memory technology being deployed may require a different sequence of fabrication steps than the implementation of supporting peripheral circuitry such as logic for address decoders, state machines, and command decoders. As a result of the need to support the manufacturing steps of both the memory array and the peripheral circuitry, the produ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/112H01L21/768H01L23/528
CPCH01L21/76898H01L21/76885H01L23/5283H01L23/5286H10B20/00H10B41/10H10B43/10H10B41/27H10B43/27H10B53/30H10B53/10H10B53/20H10B53/40H10B53/50
Inventor 叶腾豪胡志玮吕函庭
Owner MACRONIX INT CO LTD