Standard cell library construction method based on quadratic fitting model

Abstract

The invention discloses and protects a standard cell library construction method based on a quadratic fitting model, and the method comprises the steps: introducing a process fluctuation random variable into a standard cell delay model, quantifying the impact on delay from process fluctuation through statistical static timing analysis, carrying out the modeling of cell delay through adoption of aquadratic iteration method, and constructing a standard cell statistical library; in a unit layer, a plurality of working condition scenes are firstly set, serving unit delay obtained through SPICE simulation under different working conditions as training data, modeling delay distribution of circuit units, and establishing a secondary model of the unit delay about the working conditions through secondary nonlinear regression; regarding process parameter fluctuation as a random variable following Gaussian distribution, forming a unit delay model through adoption of a quadratic fitting method, and fitting a multivariate function of a delay model coefficient relative to a working condition by applying a multivariate Newton iteration method; and repeating the process for different standard units under the SMIC28nm process, and constructing a standard unit statistical library.

Description

technical field [0001] The invention belongs to the field of integrated circuit design automation (EDA), in particular to a method for constructing a standard cell library based on a quadratic fitting model. Background technique [0002] Timing analysis is the cornerstone of VLSI design and optimization. Advanced timing analysis tools ensure that the designed chips meet timing constraints. As the integrated circuit process enters the deep sub-micron field, static timing analysis of circuits at 28nm process nodes and more advanced processes is extremely sensitive to parameter changes under conditions such as manufacturing process, power supply voltage, and temperature (PVT). As the power supply voltage decreases, the sensitivity of the chip is further enhanced, and the circuit becomes more and more susceptible to fluctuations in process parameters, and the circuit delay increases rapidly to maintain sufficient timing margins to avoid timing path failures. Process parameter f...

AI Technical Summary

Problems solved by technology

However, the existing model methods still have some deficiencies in the quantification process of fluctuation parameters and the accuracy of model establishment.

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