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Test piece for optimizing fan-out package metal interconnection process and test method thereof

A metal interconnection and test piece technology, applied in semiconductor/solid-state device testing/measurement, electrical components, electrical solid-state devices, etc., can solve the problems of inaccurate measurement of contact resistance, economic losses, etc., to help R&D and production activities, simplify Structural design, convenient and fast manufacturing effect

Pending Publication Date: 2021-01-22
杭州晶通科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Purpose of the invention: The purpose of the present invention is to solve the problem that the existing packaging process test needs to rely on regular chips, and if it is defective, it will cause large economic losses and the existing contact resistance cannot be accurately measured

Method used

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  • Test piece for optimizing fan-out package metal interconnection process and test method thereof
  • Test piece for optimizing fan-out package metal interconnection process and test method thereof
  • Test piece for optimizing fan-out package metal interconnection process and test method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] Such as Figure 4 to Figure 8 As shown, the 300mm test piece is taken as an example, but other sizes of test pieces (such as 150mm, 200mm round test pieces, or other sizes of square test pieces) can also be made, a metal interconnection for optimizing fan-out packaging The test piece of the process includes a circular wafer base 100 (made of epoxy resin) and at least five groups of simplified chipsets arranged on the wafer base 100, and the five groups of simplified chipsets are respectively arranged at the center of the wafer base Positions and four positions evenly spaced along its circumference, each set of simplified chipsets includes five simplified chips 110 arranged in a cross star shape, the simplified chips 110 are simplified chips 110 with only the electrical connection structure removed , each simplified chip 110 is provided with a plurality of identical metal pad chains corresponding to the pads, each metal pad chain is composed of at least 100 pairs of pads...

Embodiment 2

[0052] A method for testing a test piece for optimizing a fan-out packaging metal interconnection process, comprising the following steps:

[0053] 1) Arranging and setting the simplified chips according to the position on the corresponding wafer substrate, and setting pad chains on the surface of the simplified chip corresponding to the exposed pads;

[0054] 2) Generate one or more layers of organic passivation protection layer under the process conditions corresponding to the required test, and form metal wiring for interconnection between pad pairs in the groove formed by the organic passivation protection layer;

[0055] 3) In each metal pad chain, before the first pair of pads, connect the pads for power supply through bridge metal lines, and also connect the pads for power supply through bridge metal lines after the last pair of pads. plate;

[0056] 4) The two current probes of the resistance testing instrument are respectively connected to the contacts of the metal w...

Embodiment 3

[0065] When the Rc of the test is obtained, if it is necessary to test whether the process environment is in a normal state, the Rc value obtained in step 4) can be used as the benchmark Rc value, and then the prepared test piece is placed under a specific working condition and measured again , to get the test Rc value, and then compare the two obtained Rc values ​​to judge the influence of the current working conditions on the Rc value for further optimization.

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Abstract

The invention discloses a test piece for optimizing a fan-out package metal interconnection process, which comprises a circular wafer substrate and at least five simplified chip groups arranged on thewafer substrate, and the five simplified chip groups are respectively arranged at the circle center position of the wafer substrate and are uniformly arranged at four positions along the circumferential direction of the wafer substrate. Each simplified chip group comprises five simplified chips arranged in a cross star shape, the simplified chips are simplified chips without chip function parts and only with electric connection structures reserved, 30 identical metal bonding pad chains corresponding to bonding pads are arranged on each simplified chip, each metal bonding pad chain is composedof at least 100 pairs of bonding pads, and each pair of bonding pads is connected through a bridging metal wire. The invention also discloses a test method of the test piece. By adopting the design scheme provided by the invention, the 'contact resistance' of the metal bonding pad chains on the test piece under a real condition process can be measured, and an optimal process condition can be conveniently found out.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a test piece and a testing method thereof for optimizing a fan-out package metal interconnection process. Background technique [0002] Wafer-level fan-out packaging (FOWLP), as an advanced packaging technology platform, is becoming the first choice for semiconductor advanced packaging by virtue of its excellent packaging performance, advantages of miniaturization and integrated packaging, and flexible and diverse 2D or 3D packaging forms. The development trend has won widespread attention and vigorous development in the industry. [0003] In the fan-out package, a variety of organic materials are widely used in the reconstituted wafer or fan-out package (for example, the plastic package is an epoxy resin organic material, and the dielectric material in the rewiring layer is polyimide) Organic substances), these organic substances often quickly absorb a large amo...

Claims

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Application Information

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IPC IPC(8): H01L23/485H01L21/66H01L21/60
CPCH01L22/14H01L23/4824H01L24/03H01L2224/0231H01L2224/02333H01L2224/02373H01L2224/02379H01L2224/02381
Inventor 王新蒋振雷
Owner 杭州晶通科技有限公司