Digital background self-calibration circuit structure and method of single-channel high-speed high-precision SAR ADC

Abstract

The invention discloses a digital background self-calibration circuit structure and method for a single-channel high-speed high-precision SAR ADC, and the structure comprises a bootstrap switch module, a capacitor array module, a comparator module, a register module, an SAR logic control module, and a digital calibration module. The bootstrap switch module is used for controlling the transmissionof an input signal; the capacitor array module is used for obtaining an error voltage and obtaining a sampling signal; the comparator module is used for comparing the voltages of the sampling signalsat different ends; the register module is used for storing the actual weight of the capacitor array module; the SAR logic control module is used for controlling a capacitor at the switch end of the capacitor array module to perform switch switching; and the digital calibration module is used for performing mathematical operation on an output result of the comparator module to obtain an error weight and an actual weight of the capacitor array module. According to the calibration method, the weight value of the high-weight-bit capacitor is effectively calibrated, and the establishment precisionof the high-weight-bit capacitor is improved, so that the data conversion rate is improved.

Description

technical field [0001] The invention belongs to the field of analog-to-digital conversion circuits, and in particular relates to a single-channel high-speed and high-precision SAR ADC digital background self-calibration circuit structure and method. Background technique [0002] Among various analog-to-digital converters, SAR ADC (Successive Approximation Register Analog-to-digital Converter) can achieve relatively high precision without consuming too much power, and is hardly affected by the process Shrinking the limit, has the potential to improve energy efficiency and speed in deep submicron CMOS processes. [0003] Capacitance matching is a key operation to realize high-speed and high-precision SAR ADC. The mismatch is generally affected by the manufacturing process and physical circuit design, including random mismatch caused by device size deviation, line width, doping concentration, and oxide layer thickness. System mismatches caused by factors including temperature ...

AI Technical Summary

Problems solved by technology

Improving matching by increasing the overall capacitor size can severely limit the data conversion speed of the ADC

Some mismatch can be reduced by proper layout and layout, but it is still very difficult to achieve more than 10-bit accuracy

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