The invention relates to a latch circuit. The latch circuit comprises a preamplifier, a comparison latch body, a first pair of reset tubes, a second pair of reset tubes, and a pair of switch tubes, wherein the preamplifier amplifies an input differential signal, the comparison latch body is connected with the preamplifier and performs compared latch on the amplified differential signal, the firstpair of reset tubes are connected with an output of the comparison latch body and a power supply, the second pair of reset tubes are connected with a drain of an input pair tube of the preamplifier and a power supply, the drain of the input pair tube of the preamplifier is grounded through the pair of switch tubes, gates of the two pairs of reset tubes receive a clock signal, a gate of the pair ofswitch tubes receives a delayed clock signal of the clock signal, the two pairs of reset tubes are used for enabling the comparison latch body to work in a linear area when the clock signal changes from low to high, and the pair of switch tubes helps reduce one tube for the ground path of the comparison latch body in work. The impact of circuit mismatch on comparison accuracy is lowered, the working time of a comparator is reduced, and the bit error rate in design of an analog-to-digital converter caused by the latch comparator is lowered.