Phase-locked loop circuit

Abstract

The invention discloses a phase-locked loop circuit. The phase-locked loop circuit comprises a delay phase-locked loop and a subsampling phase-locked loop, the delay phase-locked loop is used for locking a first reference clock and a second reference clock to an input clock, and comprises a phase correction circuit, an integrator and a first sampling phase detection circuit. The subsampling phase-locked loop is configured to generate an output clock at a predetermined phase-locked loop frequency, and the output clock is phase-locked to a first reference signal, and includes a second subsampling phase detection circuit, a phase frequency detection circuit, a voltage-controlled oscillator, and a first frequency eliminator. The phase correction circuit operates in a duty cycle adjustment modein which the integrator generates a first control signal according to a first reference clock and a second reference clock, and a delay locked loop mode in which the integrator generates a second control signal according to a second reference clock. In the delay locked loop mode, the phase correction circuit adjusts the input clock according to the second control signal to generate a first reference clock and a second reference clock.

Description

technical field [0001] The invention relates to a phase-locked loop circuit, in particular to a phase-adjusting circuit capable of operating in a duty cycle adjustment mode and a delay phase-locked loop mode, and a phase-frequency detection circuit for precisely controlling a predetermined dead time. Background technique [0002] Phase-locked loop (PLL) is a frequency and phase synchronization technology realized by the feedback (Feedback) control principle, and its function is to keep the clock output by the circuit synchronized with the external reference clock. When the frequency or phase of the reference clock changes, the phase-locked loop will detect this change and adjust the output clock through its internal feedback system until the two are re-synchronized. This synchronization is also called "phase-locked" ( Phase-locked). [0003] In a conventional PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N 2 , and this factor dominates the phase...

AI Technical Summary

Problems solved by technology

[0004] However, the above circuit has a single function and cannot be operated in different modes for different applications

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