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Novel improved butterfly unit algorithm structure for FFT processor chip design

A butterfly unit and chip design technology, applied in the field of FFT processors, can solve problems such as FFT processor condition limitations, achieve the effects of low hardware overhead, simplified control logic, and reduced hardware resource consumption

Pending Publication Date: 2021-02-12
HEBEI NORMAL UNIV FOR NATTIES
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Problems solved by technology

[0004] The purpose of the present invention is to provide a new improved butterfly unit algorithm structure for FFT processor chip design, to solve the problem of conditional limitations in the optimal design of the current FFT processor proposed by the above-mentioned background technology

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  • Novel improved butterfly unit algorithm structure for FFT processor chip design
  • Novel improved butterfly unit algorithm structure for FFT processor chip design
  • Novel improved butterfly unit algorithm structure for FFT processor chip design

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Embodiment Construction

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiment is only a mechanism embodiment of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0021] see Figure 1-Figure 4 , the present invention provides a technical solution: a new improved butterfly unit algorithm structure for FFT processor chip design:

[0022] Such as figure 1 As shown, it is the original butterfly unit structure, (a) is type I, (b) is type II, where xr(n) and xr(n+N / 2) are the real part of the input complex sequence, xi(n ) and xi(n+N / 2) are the imaginary part of the input complex sequence, zr(n) and zr(n+N / ...

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Abstract

The invention discloses a novel improved butterfly unit algorithm structure for FFT (Fast Fourier Transform) processor chip design, which comprises a module twiddle factor and a control logic'r ', specific module twiddle factors and extra control logic'r 'are added on the basis of an original butterfly-shaped unit framework to form a novel improved butterfly-shaped unit framework model, and a popular radix-2k algorithm and an SDF assembly line framework are adopted on the design of an FFT processor chip. According to the novel improved butterfly-shaped unit algorithm structure for FFT processor chip design provided by the invention, the focus is put on the improvement of the basic unit butterfly-shaped unit forming the FFT processor, and the hardware overhead and power consumption of the FFT processor are reduced by simplifying the complexity of subsequent twiddle factors; and a new idea is provided for the design of the FFT processor with low power consumption and low hardware overhead under the background of the new information era, and the novel improved butterfly unit algorithm structure has important theoretical significance and engineering application value.

Description

technical field [0001] The invention relates to the technical field of FFT processors, in particular to a novel and improved butterfly unit algorithm structure used in FFT processor chip design. Background technique [0002] FFT processors are widely used in spectrum analysis, image processing, speech recognition, biomedicine, radar, filtering, wireless and wired communications and other fields. With the advent of the 5G era, various new services and application scenarios are constantly emerging, such as Internet of Vehicles, virtual reality, online games, machine-type communications, and the Internet of Things. Transmission technologies emerged, such as filter bank multi-carrier, generalized frequency division multiplexing, general filter multi-carrier and so on. As the most important module in a multi-carrier transmission system, the FFT processor consumes hardware costs and power consumption that affect the performance of the entire multi-carrier transmission system, so ...

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Application Information

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IPC IPC(8): G06F30/343
CPCG06F30/343
Inventor 于建范浩阳姚宇凤
Owner HEBEI NORMAL UNIV FOR NATTIES