MOS device and method for preventing parasitic transistor of MOS device from being turned on

Abstract

The invention provides an MOS device and a method for preventing a parasitic transistor of the MOS device from being turned on. The MOS device comprises a silicon substrate, a field oxide region, an active region, a well region, a body leading-out region, a gate dielectric layer and an H-shaped grid bar which are located above the silicon substrate, and a field injection region located at the edgeof the active region, wherein the active region comprises a source region, a drain region and a channel region, and the body leading-out region is arranged on one side of the H-shaped grid bar in thewidth direction; an injection window is arranged on the body leading-out region, and an interface region between the back surface of the field oxygen region and the silicon substrate is a heavily doped region; the doping concentration of the heavily doped region is higher than that of the well region; and the depth of the secondary ion injection is greater than or equal to the ion injection depths of the source region and the drain region. Therefore, the window is additionally arranged above the body leading-out region, secondary ion injection is carried out along the injection window, it isensured that the edge of the field oxide region has enough high doping concentration, the parasitic transistor cannot be turned on, off-state electric leakage of the MOS device is inhibited, and the electrical characteristics of the MOS device are improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices, in particular to a MOS device and a method for preventing parasitic transistors from being turned on in the MOS device. Background technique [0002] CMOS integrated circuits have many advantages such as low power consumption, fast speed, strong anti-interference ability, and high integration. Therefore, CMOS technology is the mainstream technology of large-scale integrated circuits. [0003] Whether it is based on bulk silicon or SOI substrate materials, the leakage of MOS devices themselves and each other has always been an urgent problem to be solved in the industry. Therefore, the isolation technology of MOS devices is a key technology in the integrated circuit manufacturing process. Cause leakage, breakdown, latch-up effect, etc. [0004] In the prior art, commonly used isolation process technologies include junction isolation, Local Oxidation of Silicon (LOCOS, Local Oxidatio...

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Problems solved by technology

[0005] Aiming at the problems existing in the prior art, the embodiment of the present invention provides a MOS device and a method for avoiding the turning on of the parasitic transistor of the MOS device, which is used to solve the parasitic transistor effect caused by the parasitic transistor effect introduced when the MOS device is isolated in the prior art. turn on, which in turn leads to the increase of the off-state leakage of the MOS device and the technical problem that the electrical characteristics of the MOS device are reduced

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