A photolithographic overlay mark and its preparation method

A lithography overlay and marking technology is applied in the field of lithography overlay marking and its preparation, which can solve the problems of increasing the reject rate and production cost of power semiconductor devices, reducing the manufacturing process accuracy of power semiconductor devices, disappearing or even disappearing pattern smoke. , to achieve the effect of convenient metal peeling, clear metal marking points, clear and smooth contour lines

Active Publication Date: 2022-06-24
HEYUAN CHOICORE PHOTOELECTRIC TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

During this process, due to the physical bombardment of ions and the chemical reaction during annealing, the photolithographic overlay mark is worn, and the size of the alignment mark will change, the resolution of the pattern will decrease, the step difference will decrease, the contrast will decrease, and the pattern will be smoked. Disappearance and other issues
This affects the photolithographic alignment of the photolithographic overlay marks, reduces the precision of the subsequent manufacturing process of power semiconductor devices, and increases the reject rate and production cost of power semiconductor devices

Method used

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  • A photolithographic overlay mark and its preparation method
  • A photolithographic overlay mark and its preparation method
  • A photolithographic overlay mark and its preparation method

Examples

Experimental program
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Effect test

Embodiment 1

[0038] A photolithography overlay mark is prepared by the following method:

[0039] Step S1: make a marking point pattern, the marking point pattern is the word "back"; the marking point pattern is transferred to the chip by means of uniform glue, exposure and development, and the epitaxial layer is exposed; positive photoresist is used for the uniform glue, and the thickness of the glue is: 4μm;

[0040] Step S2: Etch the epitaxial layer; use the inductively coupled plasma etching method to etch the epitaxial layer, and the etching gas is Cl 2 and BCl 3 , the etching depth is 8000 Å, and the etching angle is 80°;

[0041] Step S3: Evaporating metal marking points, the metal structure is CrAlTiPtAu; the thickness of the first layer of Cr of the metal structure is 50 Å; the thickness of the second layer of Al is 3000 Å; the thickness of the third layer of Ti is 2000 Å; the thickness of the fourth layer of Pt is 500 Å; Layer Au thickness 1000 Å.

[0042] Step S4: peel off a...

Embodiment 2

[0044] A photolithography overlay mark is prepared by the following method:

[0045] Step S1: making a marking point pattern, the marking point pattern is a "cross"; the marking point pattern is transferred to the chip by means of uniform glue, exposure and development, and the epitaxial layer is exposed; positive photoresist is used for the uniform glue, and the thickness of the glue is 3μm;

[0046] Step S2: Etch the epitaxial layer; use the inductively coupled plasma etching method to etch the epitaxial layer, and the etching gas is Cl 2 and BCl 3 , the etching depth is 6000 Å, and the etching angle is 70°;

[0047] Step S3: Evaporating metal marking points, the metal structure is CrAlTiPtAu; the thickness of the first layer of Cr of the metal structure is 20 Å; the thickness of the second layer of Al is 1000 Å; the thickness of the third layer of Ti is 500 Å; the thickness of the fourth layer of Pt is 200 Å. The fifth layer of Au is 3000 Å thick.

[0048] Step S4: peel...

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Abstract

The invention relates to the technical field of semiconductors, in particular to a photolithographic overlay mark and a preparation method thereof. The preparation method includes the following steps: step S1: making a pattern of marking points, transferring the pattern of marking points to the chip to expose the epitaxial layer; step S2: etching the epitaxial layer; step S3: evaporating metal marking points, the metal structure is CrAlTiPtAu ; The CrAlTiPtAu metal structure is a metal Cr layer, an Al layer, a Ti layer, a Pt layer, and an Au layer from bottom to top; step S4: stripping and removing glue. The photolithographic overlay mark prepared by the method provided by the invention has strong wear resistance, high resolution, is not easy to be corroded, and is extremely slightly affected by the physical bombardment of ions and the corrosion of chemical solutions; at the same time, the metal marking points of the present invention can reflect light, Make the metal marking points clearer and improve the alignment accuracy.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a photolithography overlay mark and a preparation method thereof. Background technique [0002] A semiconductor refers to a material whose electrical conductivity is between that of a conductor and an insulator at room temperature. With the advancement of science and technology and the development of society, semiconductors are widely used in integrated circuits, consumer electronics, communication systems, photovoltaic power generation, lighting, high-power power conversion and other fields. The core units of most electronic products, such as computers, mobile phones or digital recorders, are closely related to semiconductors. In the semiconductor manufacturing process, the lithography process is the core technology, and the accuracy of the overlay will directly affect the appearance and performance of the product. [0003] The traditional overlay process forms the powe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544
CPCH01L23/544
Inventor 李国强
Owner HEYUAN CHOICORE PHOTOELECTRIC TECH CO LTD
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