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Wafer-level packaging process and wafer-level packaging structure

A wafer-level packaging and process technology, which is applied in the manufacturing of electrical components, electrical solid-state devices, and semiconductor/solid-state devices, etc., can solve the problems of limited thickness, contamination of the functional area 102', and increased defective product rate of wafer packaging structures, etc. Achieve the effect of not easy to contaminate, good packaging effect and high yield

Pending Publication Date: 2021-04-16
苏州科阳半导体有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, on the one hand, if figure 2 As shown, when the roller rolls glue, especially for wafers with a large functional area, the area of ​​the support cofferdam is relatively small, and the glue is easy to fall into the groove 400 ′ formed by the support cofferdam 300 ′ and the cover plate 200 ′. Residual glue is formed, and the residual glue may pollute the functional area 102' after bonding; ' bonded on the substrate 101', such as image 3 As shown, the bonding glue 700' will be filled into the sinker 104', and the thickness of the bonding glue 700' that can be coated by the roller rolling method is limited, so when the supporting cofferdam 300' and the wafer 100' are pressed Immediately afterwards, the bonding glue 700' cannot be fully filled and a bubble 500' is generated near the pad 103', resulting in an increase in the defective rate of the final wafer package structure

Method used

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  • Wafer-level packaging process and wafer-level packaging structure
  • Wafer-level packaging process and wafer-level packaging structure
  • Wafer-level packaging process and wafer-level packaging structure

Examples

Experimental program
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Effect test

Embodiment 1

[0050] This embodiment provides a wafer-level packaging process, which can be used to package the wafer 100 . The wafer 100 includes a substrate 101 on which a plurality of functional areas 102 are distributed in a matrix, and each functional area 102 is provided with welding pads 103 around it. The wafer-level packaging process of this embodiment is especially suitable for packaging the wafer 100 whose size of the functional area 102 is not smaller than 3mm×5mm.

[0051] Such as Figure 4-Figure 8 shown (where Figure 5-Figure 8 Only the structure within a functional area 102 on the wafer 100 is shown), the wafer level packaging process includes steps:

[0052] Such as Figure 5 and Figure 6 As shown, a support cofferdam 3 is made on the cover plate 2 to form a plurality of grooves 5 distributed in a matrix. The support cofferdam 3 includes edges for surrounding the grooves 5, and the inner ends of the edges are recessed Serrated segment 31;

[0053] Such as Figure 7...

Embodiment 2

[0063] The difference between this embodiment and the first embodiment is that the covering plate 2 and the supporting cofferdam 3 are formed integrally, the covering plate 2 is a silicon chip, and a groove 5 is provided on one side of the covering plate 2 to form the supporting cofferdam 3 . Specifically, the step of opening the groove 5 on the cover plate 2 includes: using photolithography to form a region to be grooved on the surface of the silicon wafer; Grooves 5 are etched to form support dams 3 . Of course, in other embodiments, the groove 5 can also be made by laser ablation method directly on the silicon wafer, and the steps are simpler.

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Abstract

The invention relates to the technical field of semiconductor packaging, and discloses a wafer-level packaging process and a wafer-level packaging structure. A wafer comprises a substrate, a plurality of functional areas are distributed on the substrate in a matrix mode, and a welding pad is arranged around each functional area; the wafer-level packaging process comprises the steps that a supporting cofferdam is manufactured on a covering plate to form a plurality of grooves distributed in a matrix mode, the supporting cofferdam comprises edges used for forming the grooves in an enclosing mode, and sawtooth sections are arranged at the ends of the inner sides of the edges in a concave mode; bonding glue is coated on the supporting cofferdam through a silk-screen printing process; and the covering plate and the support cofferdam coated with the bonding glue are bonded on the wafer, the support cofferdam is tightly combined with the welding pads through the bonding glue, and the functional areas are accommodated in the grooves. According to the wafer-level packaging process, the functional areas are not easy to pollute, the packaging effect is good, and the rate of finished products is high. According to the wafer-level packaging structure, the wafer-level packaging process is adopted, and the packaging quality is good.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level packaging process and a wafer-level packaging structure. Background technique [0002] Compared with the traditional packaging process, the wafer-level packaging process is based on the wafer (each wafer is provided with multiple chips in a matrix) as the unit in the packaging process, and the wafer is packaged as a whole and then the chip is used as the unit. cutting. [0003] Such as figure 1 As shown, the wafer 100' includes a substrate 101', and a plurality of functional areas 102' are arranged in a matrix on the substrate 101' ( figure 1 Only the structure at one functional area 102' on the substrate 101' is shown), and several welding pads 103' are arranged around each functional area 102', and the welding pads 103' are used to realize the electrical connection between the wafer 100' and the external structure. connect. In the existing tech...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/56H01L23/10
Inventor 殷晨晖陈胜江勇虞亚运
Owner 苏州科阳半导体有限公司