Semiconductor device, packaging structure and preparation method of packaging structure
A technology of packaging structure and packaging layer, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of reducing the size of the packaging structure, the thickness of the packaging structure, and the disadvantages.
Pending Publication Date: 2021-06-04
CHANGXIN MEMORY TECH INC
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However, since the wire needs to be bent to connect with the external circuit after it is led out, enough space needs to be left for the wire to be bent between two adjacent chip units, which makes the packaging structure thicker, which is not conducive to reducing the packaging structure. size of
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[0041] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
[0042] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the description in the accompanying drawings directions for the example described above. It will be appreciated that if the illustrated device is turned over so...
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The invention provides a semiconductor device, a packaging structure and a preparation method of the packaging structure, and relates to the technical field of semiconductor packaging. The packaging structure comprises a chipset, a conductive film layer, a lead and a packaging layer; the chipset comprises a plurality of chip units which are stacked in the vertical direction, wherein at least one end of each chip unit is provided with a groove; a conductive film layer which is attached to the surface of the groove along with the shape; a lead, wherein one end of the lead is connected to the conductive film layer, and the other end extends to the outer side of the chip unit; and a packaging layer which is at least arranged among the chip units and is used for fixedly connecting the chips. According to the packaging structure, the size of the packaging structure can be reduced, and the storage capacity is improved.
Description
technical field [0001] The present disclosure relates to the technical field of semiconductor packaging, and in particular, to a semiconductor device, a packaging structure, and a method for preparing the packaging structure. Background technique [0002] With the development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller, and the requirements for the capacity of semiconductor devices are getting higher and higher. Therefore, the preparation of high-capacity, small-size semiconductor components has become the focus of research in recent years. Since the semiconductor component is directly exposed to the external environment, its structure is likely to be damaged, so it is very important for the packaging of the semiconductor component. [0003] In order to increase the capacity of the semiconductor components in the packaging structure, it is usually necessary to stack multiple chip units together and connect the chip units with...
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IPC IPC(8): H01L25/065H01L23/31H01L23/495H01L21/48
CPCH01L25/0657H01L23/3128H01L23/49544H01L21/4825H01L2224/83191H01L2224/32145H01L2224/32225H01L2224/85365H01L2224/05H01L2224/03H01L2224/73265H01L2224/48091H01L2924/15311H01L2924/00014
Inventor 张志伟
Owner CHANGXIN MEMORY TECH INC