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Interconnection structure, preparation method thereof and semiconductor structure

A technology of interconnecting structure and dielectric layer, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as reducing the performance of semiconductor structures and signal delays

Active Publication Date: 2021-06-08
CHANGXIN MEMORY TECH INC
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0003] In the related art, the interconnection structure usually includes at least one interconnection layer, and the interconnection layer includes a plurality of metal lines arranged at intervals and a dielectric layer for isolating each metal line. With the development of semiconductor structures in the direction of miniaturization and integration , so that the spacing between adjacent metal lines in the same interconnection layer is also reduced, and parasitic capacitance can be formed between adjacent metal lines. The existence of this parasitic capacitance will cause signal delay and reduce the reliability of the semiconductor structure. performance

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  • Interconnection structure, preparation method thereof and semiconductor structure
  • Interconnection structure, preparation method thereof and semiconductor structure
  • Interconnection structure, preparation method thereof and semiconductor structure

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Embodiment Construction

[0065] The inventor of the present application finds in actual work, such as figure 1 As shown, the smaller the size (such as thickness or length) of the semiconductor structure is, the vertical distance and horizontal distance between adjacent metal lines 30 in the interconnection structure 100 will also be reduced accordingly, and the distance between the adjacent metal lines Parasitic capacitances are formed that cause signal delays in the interconnect structure and degrade the performance of the semiconductor structure.

[0066] In view of the above-mentioned technical problems, embodiments of the present invention provide an interconnection structure and a manufacturing method thereof, and a semiconductor structure, by providing a gap between the insulating layer and the substrate between adjacent metal lines, that is, adjacent There is an air gap between the metal lines, so that the dielectric constant of the air is lower than that of the insulating layer, and the capaci...

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Abstract

The invention provides an interconnection structure, a preparation method thereof and a semiconductor structure, and relates to the technical field of semiconductors, the interconnection structure comprises a substrate, a dielectric layer and an insulating layer, the dielectric layer and the insulating layer are arranged on the substrate, and a plurality of metal wires are arranged in the dielectric layer at intervals; a groove is formed in the dielectric layer between the adjacent metal wires, and the groove bottom of the groove exposes the surface of the substrate; the insulating layer is provided with extension parts extending into the grooves, and gaps are formed between the extension parts and the substrate. The gaps are formed between the insulating layer between the adjacent metal wires and the substrate, namely, the air gaps is formed between the adjacent metal wires, so that the dielectric constant of air is smaller than that of the insulating layer, the capacitance value of stray capacitance between the adjacent metal wires can be reduced, the signal delay of the interconnection structure is reduced, and the performance of the semiconductor structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an interconnection structure, a preparation method thereof, and a semiconductor structure. Background technique [0002] In the process of semiconductor structure fabrication, the interconnection structure is an indispensable structure in the semiconductor structure, for example, dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM)), the formed dynamic random access memory usually includes a core storage area and a peripheral The circuit area, wherein the core storage area is used to set a plurality of storage units for storing data information, the core storage area and the peripheral circuit area usually include an interconnection structure, and the interconnection structure is used for electrical connection with the storage unit, so that The storage unit completes storage or reading of data information. [0003] In the related art, the inter...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/528H01L21/768
CPCH01L23/528H01L21/7682H01L2221/1047
Inventor 朱德龙
Owner CHANGXIN MEMORY TECH INC