Interconnect structure and preparation method thereof, semiconductor structure

Abstract

The invention provides an interconnection structure and a preparation method thereof, a semiconductor structure, and relates to the field of semiconductor technology. The interconnection structure includes a substrate, a dielectric layer provided on the substrate, and an insulating layer. A plurality of metal strips are spaced in the dielectric layer. lines; a groove is provided in the dielectric layer between adjacent metal lines, and the bottom of the groove exposes the surface of the substrate; the insulating layer has an extension extending into the groove part, and there is a gap between the extension part and the base. The present invention provides a gap between the insulating layer between adjacent metal lines and the substrate, that is, an air gap between adjacent metal lines, so that the dielectric constant of air can be used to be smaller than the dielectric of the insulating layer. Constant, reducing the capacitance value of the parasitic capacitance between adjacent metal lines to reduce the signal delay of the interconnect structure, thereby improving the performance of the semiconductor structure.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, and in particular, to an interconnection structure, a preparation method thereof, and a semiconductor structure. Background technique [0002] In the manufacturing process of semiconductor structures, the interconnection structure is an indispensable structure in the semiconductor structure, such as dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM). The formed dynamic random access memory usually includes a core storage area and a peripheral Circuit area, in which the core storage area is used to set up multiple storage units for storing data information. The core storage area and the peripheral circuit area usually include interconnection structures, and the interconnection structures are used to electrically connect with the storage units so that The storage unit completes the storage or reading of data information. [0003] In the related art, the...

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Problems solved by technology

[0003] In the related art, the interconnection structure usually includes at least one interconnection layer, and the interconnection layer includes a plurality of metal lines arranged at intervals and a dielectric layer for isolating each metal line. With the development of semiconductor structures in the direction of miniaturization and integration , so that the spacing between adjacent metal lines in the same interconnection layer is also reduced, and parasitic capacitance can be formed between adjacent metal lines. The existence of this parasitic capacitance will cause signal delay and reduce the reliability of the semiconductor structure. performance

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