A Fast Delayed Signal Destruction Filtering Method

A technology of delayed signal and cancellation, applied in harmonic reduction devices, AC networks to reduce harmonics/ripple, automatic power control, etc., can solve large filter delays, increase the amount of calculation, and affect the dynamic performance of the system and other problems to achieve the effect of eliminating harmonic interference and improving dynamic performance

Active Publication Date: 2022-04-08
SHANDONG INST OF BUSINESS & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the ability of a single delay operator to eliminate harmonics is limited, and multiple different delay operators need to be cascaded to eliminate all target harmonics. However, this increases the amount of calculation and causes a large filtering delay, which affects the system dynamic performance

Method used

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  • A Fast Delayed Signal Destruction Filtering Method
  • A Fast Delayed Signal Destruction Filtering Method
  • A Fast Delayed Signal Destruction Filtering Method

Examples

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Embodiment Construction

[0035] The principles and features of the present invention are described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

[0036] Figure 1a FDSC(m i , n i ), where u(t) is the current moment voltage, u(t-T / n i ) and u(t-2T / n i ) is the sampling voltage at two lag moments, u i (t) is a target sub-harmonic at time t, select m i , satisfying the relation u i (t)+u i (t-2T / n i ) = m i × u i (t-T / n i ), then you can construct Figure 1b the vector triangle shown, thus eliminating u i (t).

[0037] Its transfer function is

[0038]

[0039] In the above formula, s is the Laplacian operator.

[0040] Substitute into s=jhω 1 , the frequency response of FDSC amplitude and phase angle is obtained as

[0041] FDSC(m,n)[jhω 1 ]=(2cos(2hπ / n)-m)e -j2hπ / n (2)

[0042] It can be seen that when 2cos(2hπ / n i )-m i =0, the amplit...

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Abstract

The invention discloses a fast time-delayed signal destructive filtering method, which divides the target harmonic into sub-harmonics with a certain frequency variation law; Triangulation eliminates this sub-harmonic; cascading different delay operators suppresses all target harmonics. The method can quickly eliminate target harmonics and accurately extract fundamental wave voltage components in the case of severe grid voltage distortion. Compared with the traditional delay cancellation method, this method has a shorter filtering time and has a stronger ability to filter out harmonics.

Description

technical field [0001] The invention relates to the field of grid-connected power generation, in particular to a fast delay signal destructive filtering method. Background technique [0002] Phase-locked loop is widely used to estimate synchronous information such as the amplitude and phase angle of grid voltage, and is one of the key technologies for grid-connected power generation. However, the grid background harmonics affect the accurate extraction of fundamental voltage components, resulting in phase-locking deviation. Therefore, effective filtering of harmonics is an important prerequisite for accurate grid connection of phase-locked loops. [0003] Existing filtering techniques are mainly divided into two categories: [0004] The first type is the loop filter, which is located inside the closed loop of the phase-locked loop and after the phase detector. At this time, the main odd harmonics in the grid voltage have become even harmonics after passing the phase detect...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/099H02J3/01
CPCH03L7/099H02J3/01Y02E40/40
Inventor 李希年姜保红华臻郭文孙静
Owner SHANDONG INST OF BUSINESS & TECH
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