Groove type field effect transistor structure and preparation method thereof
A field-effect transistor, trench-type technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as the difficulty of effectively extracting the body region and source, and the difficulty of continuing to reduce the size of the original cell. The effect of early breakdown and cell size reduction
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Embodiment 1
[0077] like figure 1 As shown, the present invention provides a method for preparing a trench field effect transistor structure, comprising the steps of:
[0078] providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate;
[0079] A plurality of first grooves arranged in parallel and at intervals and a plurality of second grooves arranged in parallel and at intervals are formed in the epitaxial layer, wherein the first grooves and the second grooves are intersected, so as to enclosing several implantation regions based on the adjacent first trenches and the second trenches;
[0080] A first gate dielectric layer is formed on the inner wall of the first trench, a first gate structure is formed on the first gate dielectric layer, the first gate structure is filled in the first trench, and A second gate dielectric layer is formed on the inner wall of the second trench, a second gate structure is formed on the second gate dielectric layer...
Embodiment 2
[0107] like Figure 10-13 shown, and see Figure 1-9 , the present invention also provides a trench type field effect transistor structure, the field effect transistor structure is preferably prepared by the preparation method of the trench type field effect transistor structure in Embodiment 1 of the present invention, of course, it can also be prepared by other methods, The trench field effect transistor structure includes: a semiconductor substrate 100, an epitaxial layer 101, a first trench 102 and a second trench 103 formed in the epitaxial layer 101, a first gate dielectric layer 105, a second A gate dielectric layer (not shown in the figure), a first gate 111, a second gate (not shown in the figure), a body region 107, a source 109 and a source electrode structure 114, wherein:
[0108] The semiconductor substrate 100 may be a substrate of the first doping type. In this example, it is selected as an N-type doped substrate. In addition, in an example, it may be a heavil...
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