Novel FPGA structure of power gating technology based on anti-fuse device control

Abstract

The invention provides a novel FPGA structure of a power gating technology based on anti-fuse device control. Through the design of power gating, the objects of improving the chip yield, reducing the manufacturing cost of an FPGA chip and reducing the static power consumption of the FPGA are achieved. The on and off of a power switch device in the power gating technology are controlled by adopting an anti-fuse circuit. The control circuit has the advantages that the power-on and power-off sequence is controllable, and the yield of chips is improved.

Description

technical field [0001] The present invention relates to integrated circuit technology, and more specifically relates to a novel FPGA structure design based on power gating technology controlled by an antifuse device. Background technique [0002] The advancement of science and technology has continuously promoted the rapid development of my country's semiconductor industry. Field Programmable Gate Array (Field Programmable Gate Array, FPGA), as a branch of semiconductor devices, has gradually evolved into the core device of digital systems, and has been widely used in industrial control, automotive electronics, communications, aerospace, prototype verification and other fields. [0003] In the field of semiconductors, integrated circuit manufacturing technology has entered the era of nanotechnology. After the process size of semiconductor devices is lower than 90nm, static power consumption accounts for an increasing proportion of the total power consumption of FPGA. Power c...

AI Technical Summary

Problems solved by technology

[0003] In the field of semiconductors, integrated circuit manufacturing technology has entered the era of nanotechnology. After the process size of semiconductor devices is lower than 90nm, the static power consumption in the total power consumption of FPGA The proportion is getting bigger and bigger. Power consumption not only affects the service life of the battery, but also increases the heat dissipation cost, power distribution cost, and packaging cost of the chip, thereby reducing the market competitiveness of the chip.

And excessive power consumption will also reduce the reliability of the chip through temperature rise and other ways, such as changes in electrical parameters, electron migration, silicon chip connection failures and packaging failures, etc.

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