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Method for forming semiconductor structure and semiconductor structure

A semiconductor and barrier layer technology, which is applied to the formation method of semiconductor structures and the field of semiconductor structures, can solve the problems of lowering the yield of semiconductor structures, increasing the contact resistance of bit line contact structures, affecting the electrical properties of semiconductor structures, etc., and increasing the contact area. Large, increase the bottom area, reduce the effect of contact resistance

Active Publication Date: 2022-05-31
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] As the line width of DRAM (Dynamic Random Access Memory, DRAM) gradually decreases, the size of the bit line structure to be formed decreases, resulting in a decrease in the size of the bit line contact structure to be formed. The reduction in the size of the line contact structure leads to an increase in the contact resistance of the bit line contact structure, thereby affecting the electrical properties of the subsequently formed semiconductor structure, which in turn leads to a decrease in the yield of the semiconductor structure

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  • Method for forming semiconductor structure and semiconductor structure
  • Method for forming semiconductor structure and semiconductor structure
  • Method for forming semiconductor structure and semiconductor structure

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Embodiment Construction

[0027] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing

[0030] Referring to FIG. 1, a substrate 100 is provided, and the substrate 100 includes a shallow trench isolation structure 110, an active region 120 and a word line junction

[0031] The material of the substrate 100 may include silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.; in this embodiment

[0032] Specifically, the plurality of active regions 120 in the substrate 100 are arranged in parallel and spaced apart from each other. It should be noted that in the base 100

[0034] Referring to FIG. 2 and FIG. 3, a dielectric layer 101 is formed on the surface of the substrate 100; wherein, referring to FIG. 2, part of the dielectric layer 101 is also

[0035] Referring to FIG. 4 and FIG. 5, a mask layer 102 is formed on the surface of the dielectric layer 101, and the mask layer 102 has...

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Abstract

Embodiments of the present invention provide a method for forming a semiconductor structure and a semiconductor structure, wherein the method for forming a semiconductor structure includes: providing a substrate, forming a dielectric layer on the surface of the substrate; forming a mask layer on the surface of the dielectric layer, and forming a mask layer in the mask layer A first opening through the thickness of the mask layer; a first barrier layer is formed on the sidewall of the first opening, and the first barrier layer surrounds a second opening; a second barrier layer filling the second opening is formed; a first etching process is adopted , remove the first barrier layer and the second barrier layer until the first barrier layer or the second barrier layer is completely removed; remove the dielectric layer and part of the substrate exposed by the first opening to form a bit line contact opening, the bit line contact opening The bottom has a raised area and a sunken area, and the raised area and the sunken area have a height difference; the embodiment of the present invention aims to reduce the contact resistance of the bit line contact structure by increasing the bottom contact area of ​​the bit line contact opening.

Description

Method for forming semiconductor structure and semiconductor structure technical field The present invention relates to the field of semiconductor structure manufacturing, in particular to a method for forming a semiconductor structure and a semiconductor structure. Background technique As the line width of dynamic random access memory (Dynamic Random Access Memory, DRAM) gradually decreases small, the size of the bit line structure to be formed is reduced, resulting in a reduction in the size of the bit line contact structure that needs to be formed, while the size of the bit line contact structure is reduced. The reduction in the size of the contact structure leads to an increase in the contact resistance of the bit line contact structure, which affects the subsequent formation of the semiconductor structure. electrical properties, which in turn leads to a decrease in the yield of semiconductor structures. Under the premise that the size of the bit line contact s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/108H10B12/00
CPCH10B12/34H10B12/053H10B12/482H01L21/28185H01L21/76814H01L21/76831H01L21/76843H01L23/528
Inventor 穆天蕾
Owner CHANGXIN MEMORY TECH INC