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Stacked semiconductor device packaging structure and preparation method thereof

A device packaging and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid device manufacturing, semiconductor/solid device components, etc., can solve problems such as fracture, metal wire offset, collapse, etc., to avoid offset and reduce metal The use of bonding wires and the effect of improving reliability

Pending Publication Date: 2021-07-20
湖南越摩先进半导体有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This connection method makes the welding wires in the plastic sealing process, there may also be risks such as metal welding wire offset, collapse, breakage, etc.

Method used

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  • Stacked semiconductor device packaging structure and preparation method thereof
  • Stacked semiconductor device packaging structure and preparation method thereof
  • Stacked semiconductor device packaging structure and preparation method thereof

Examples

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Embodiment Construction

[0036] The present invention is further detailed in conjunction with the accompanying drawings and examples. It will be appreciated that the specific embodiments described herein are merely illustrative of the invention and are not limited thereto. It will also be noted that in order to facilitate the description, only the parts associated with the present invention are shown in the drawings rather than all structures.

[0037] figure 1 For a schematic diagram of a packaging structure of a stacked semiconductor device provided by the embodiment of the present invention, see figure 1 The stacked semiconductor device package includes: the substrate 110; the N-chip 120 disposed on the substrate 110, the first chip 120 and the substrate 110 are minimized, the closer to the substrate 110, the larger the size of the chip 120; The chip 120 is located away from the surface of the substrate 110 and is provided with a connecting portion 121 in the surface of the substrate 110, and the kth ...

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PUM

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Abstract

The invention discloses a stacked semiconductor device packaging structure and a preparation method thereof. The stacked semiconductor device package structure includes: a substrate, n chips , conductive connectors , a plastic package body and a redistribution layer; the n chips are stacked on the substrate, the distance between the first chip and the substrate is minimum, and the closer the first chip is to the substrate, the larger the size of the chip is; connecting parts are arranged on the surface, away from the substrate, of the kth chip and the surface, close to the substrate, of the kth chip, and the kth chip is connected with the (k-1) th chip through the connecting part close to the surface of the substrate; wherein k is greater than or equal to 2 and less than or equal to n, and k and n are positive integers; the conductive connectors are arranged on the substrate and is positioned around the chip; the plastic package body packages the chips and the conductive connectors in a plastic mode, and the conductive connectors and the connecting parts, away from the surface of the substrate, of the nth chip are exposed out of the plastic package body; and the redistribution layer is connected with the exposed conductive connector and the exposed connecting part. The effect of improving the reliability of the stacked semiconductor device packaging structure is achieved.

Description

Technical field [0001] Embodiments of the present invention relate to the semiconductor technology, and more particularly to a stacked semiconductor device package structure and a preparation method thereof. Background technique [0002] With the development of semiconductor manufacturing technology, there is now a significant need to connect multiple semiconductor chip stacks to achieve more features. [0003] Currently, traditional overlapping modes are connected to the weldings and substrates to connect chip pads and substrates using metal welding wires. This connection allows the welding wire in the plastic process, and there may be risks such as metal welding wire offset, collapse, and break. Inventive content [0004] The present invention provides a stacked semiconductor device package structure and a preparation method thereof to achieve the reliability of improving the semiconductor device. [0005] In the first aspect, the embodiment of the present invention provides a...

Claims

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Application Information

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IPC IPC(8): H01L25/065H01L21/98H01L23/31H01L21/50H01L21/56
CPCH01L21/50H01L21/56H01L23/3114H01L23/3121H01L25/0657H01L25/50H01L2225/0651H01L2225/06513H01L2225/06527H01L2225/06568
Inventor 卞龙飞
Owner 湖南越摩先进半导体有限公司
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