Stacked semiconductor device packaging structure and preparation method thereof
A device packaging and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid device manufacturing, semiconductor/solid device components, etc., can solve problems such as fracture, metal wire offset, collapse, etc., to avoid offset and reduce metal The use of bonding wires and the effect of improving reliability
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[0036] The present invention is further detailed in conjunction with the accompanying drawings and examples. It will be appreciated that the specific embodiments described herein are merely illustrative of the invention and are not limited thereto. It will also be noted that in order to facilitate the description, only the parts associated with the present invention are shown in the drawings rather than all structures.
[0037] figure 1 For a schematic diagram of a packaging structure of a stacked semiconductor device provided by the embodiment of the present invention, see figure 1 The stacked semiconductor device package includes: the substrate 110; the N-chip 120 disposed on the substrate 110, the first chip 120 and the substrate 110 are minimized, the closer to the substrate 110, the larger the size of the chip 120; The chip 120 is located away from the surface of the substrate 110 and is provided with a connecting portion 121 in the surface of the substrate 110, and the kth ...
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