Power semiconductor devices with improved hot carrier injection
A technology of power semiconductors and hot carriers, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problem of reducing switching losses, slowing down device switching speeds, and not reducing hot carriers injected into dielectric tanks for a long time Reliability issues and other issues, to achieve the effect of reducing switching loss and reducing gate-to-drain parasitic capacitance Cgd
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Embodiment 1
[0069] like Figure 4 As shown, a power LDMOS device with a dielectric groove includes: a substrate 101 of a second doping type, a drift region 102 of a first doping type on the substrate 101, and a dielectric groove on the surface of the drift region 102 107;
[0070] The dielectric trench 107 includes a drain field plate 115, a shielding gate electrode 120, the drain field plate 115 is located on the side of the dielectric trench 107 close to the drain, and the shielding gate electrode 120 is entirely located between the gate and drain electrodes and is located in the dielectric trench 107 On the inner side close to the source, the shielding gate electrode 120 is provided with a first oxide layer 131 on the side close to the source, the bottom of the shielding gate electrode 120 is provided with a third oxide layer 133, and the drain field plate 115 is provided on the side close to the drain. The second oxide layer 132; the drain field plate 115 in the dielectric trench is ...
Embodiment 2
[0074] like Figure 5 As shown, a power LDMOS device with a dielectric groove is used. In this embodiment, on the basis of Embodiment 1, a first doping type is introduced between the dielectric groove 107 and the first body region 103 JFET region 121 . The doping concentration of the JFET region 121 is higher than that of the drift region 102 .
[0075] In this technical solution, the doping type of the substrate 101 , the first body region 103 and the second body region 104 is the second type doping, the drain region 106 , the source region 105 , the drift region 102 and the JFET region 121 are The doping type is the first type doping. The drain electrode 110 is connected to a high potential, the source electrode 111 is connected to a low potential or ground, and when the first gate electrode 114 is connected to a high potential, a channel is formed on the surface of the first body region 103, the device is turned on, and the drain field in the dielectric trench 107 The pl...
Embodiment 3
[0087] like Image 6 As shown, for a power LDMOS device with a dielectric groove, on the basis of Embodiment 1, a second gate electrode 141 is provided under the shielding gate electrode 120; the first body region 103 extends to the first Oxide layer 131 .
[0088] That is, compared with Embodiment 1, the cross-sectional area of the first body region 103 is larger. The length of the first gate electrode 114 in this embodiment is shorter than that of the previous embodiment because a part of the channel length is transferred to the corresponding position on the left side of the second gate electrode 141 in the dielectric trench 107 .
[0089] In this technical solution, the doping type of the substrate 101 , the first body region 103 and the second body region 104 is the second type doping, the JFET region 121 , the drain region 106 , the source region 105 and the drift region 102 The doping type is the first type doping. The drain field plate 115 in the dielectric trench ...
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