Power semiconductor device with improved hot carrier injection

Abstract

According to the power semiconductor device for improving hot carrier injection provided by the invention, the drain electrode field plate is introduced at one side of the drain electrode in the dielectric groove, is connected with the drain electrode and has the same potential with the drain electrode, so the hole injection effect at the drain electrode side of the dielectric groove is improved; a shield gate field plate is introduced into one side of the source electrode in the dielectric groove and is connected with the source electrode or the ground to form a shield gate, so the gate-drain parasitic capacitance Cgd is reduced, and the electron injection effect on one side of the source electrode of the dielectric groove is improved; through a deep groove etching method, carriers are enabled to avoid the side wall of a medium groove on a path, and hot carrier injection can also be improved. The invention provides a power semiconductor device structure with long-term reliability, low on-resistance and high switching speed for a power semiconductor device with a medium groove.

Description

technical field [0001] The invention belongs to the field of power semiconductors, and more specifically relates to a power semiconductor device for improving hot carrier injection. [0002] technical background [0003] Power semiconductors are widely used in power integrated circuits, especially DC-DC, AC-DC and other drive circuits. Among them, power LDMOS (Laterally-Diffused Metal-Oxide Semiconductor) devices have attracted much attention due to their easy integration. During the development of LDMOS, the purpose of many innovative technologies is to improve the figure of merit FOM=BV of LDMOS 2 / R on-sp (FOM, Figure Of Merit), BV and R on-sp There are many ways to improve the compromise relationship: Super Junction (SJ, SuperJunction), Reducing Surface Field Technology (RESURF, REduce SURface Field), Silicon Local Oxidation Isolation (LOCOS, Local Oxidation of Silicon), Shallow Trench Isolation (STI, Shallow Trench Isolation), silicon on insulator (SOI, Silicon On Ins...

AI Technical Summary

Problems solved by technology

[0008] A conventional LDMOS structure with a dielectric trench such as figure 2 As shown, by extending the first gate electrode 114 above a part of the drift region 102, the second gate electrode 141 is embedded in the dielectric groove 107 and acts as a field plate. In the case of conduction, the drift region 102 is close to a part of the high potential gate electrode. An accumulation layer will be formed on the side of the dielectric tank. The design of this structure reduces the on-resistance, but also improves the hot carrier injection effect on the source side of the dielectric tank. On the other hand, the extension of the first gate electrode 114 makes the gate electrode and the The overlapping area of ​​the drift region 102 becomes larger, which will lead to the gate-drain parasitic capacitance C of the LDMOS device gd The increase of the device will cause the switching speed of the device to slow down and the switching power to increase.

[0009] A conventional LDMOS structure with a dielectric trench such as image 3 As shown, by introducing the Faraday cover 113 connected to the source terminal on the dielectric groove 107, the function of the Faraday cover is realized, the potential connection between the gate and the drain is blocked, and the gate-drain parasitic capacitance C of the LDMOS device is reduced. gd , but the disadvantage is that this design only considers the reduction of switching losses, and does not reduce the long-term reliability problems caused by hot carrier injection into the dielectric tank

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