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Semiconductor chip and its mfg. method

A semiconductor and conductor technology, applied in the field of buffer layer formation, can solve problems such as dielectric layer and component performance changes, lithographic image deformation, low wafer productivity, etc.

Inactive Publication Date: 2003-12-24
SIEMENS AG +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These limitations include low wafer throughput, non-uniformity of the polished surface and a problem related to the uniformity of polishing known as "edge rejection"
[0005] Surface non-uniformity often has an adverse effect on photolithography masks
Non-uniformity with subsequent processing leads to changes in dielectric layer and component properties
Distorts the photolithographic image, which has an undesired effect on the electronic components formed on the semiconductor chip

Method used

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  • Semiconductor chip and its mfg. method
  • Semiconductor chip and its mfg. method
  • Semiconductor chip and its mfg. method

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Embodiment Construction

[0038]The present invention describes a method for forming a buffer layer in a liner layer and separating it into a liner stop layer and a dielectric layer. If necessary, the pad stop layer can be polished, etched and processed. When the liner stop layer is no longer needed, it can be selectively removed by etching to expose the buffer layer. The buffer layer can now be processed and / or selectively etched away to expose the dielectric layer. Since the dielectric layer is preserved in the previous processing, the dielectric layer has a predetermined thickness greater than the minimum required thickness for use as a polishing or etching stop layer and can be effectively used on a semiconductor chip to produce electronic components.

[0039] Now referring to the drawings in particular in detail, the same reference numerals in all the drawings indicate similar or identical elements, starting with FIG. 2, a cross-section of the substrate 102. The substrate represents a part of the IC. ...

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Abstract

A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

Description

Technical field [0001] The present invention relates to a semiconductor device, and in particular, to a method for arranging a buffer layer in a dielectric layer to improve the control of the thickness and flatness of the dielectric and a method for forming the buffer layer. Background technique [0002] Semiconductor wafers, such as wafers made of silicon, are used as substrates for processing integrated circuit chips. With the improvement of processing technology over the years, the diameter of the wafer has increased to the current size of about 8 inches or more. Generally, a large silicon single crystal ingot is cut into wafers and is generally circular in shape. [0003] Shrinking the feature size of integrated circuits has increased the criticality of wafer flatness. Now that the use of sub-micron feature sizes is common, surface flatness takes on new importance because it is the key to improving performance. For this reason, the process control always reduces the feature s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/76H01L21/308H01L21/31H01L21/316H01L21/318H01L21/763H10B12/00
CPCH01L21/31Y10S438/97H01L21/763H01L21/3081H01L27/1087H01L27/10867H10B12/0385H10B12/0387H01L21/302
Inventor 乌尔里克·格里宁乔彻·贝因特纳卡尔·拉登斯
Owner SIEMENS AG