Semiconductor device

Abstract

The invention discloses a semiconductor device includes a memory circuit. The memory circuit comprises an array of memory cells and a plurality of input / output (I / O) circuits, the plurality of I / O circuits comprises a first group of I / O pins and a second group of I / O pins, wherein: an MxN array of one-bit memory cells of the array of memory cells are grouped into N / 2 two-column pairs of Mx1 one-bit memory cells with M being a positive integer representative of a number of rows and N being a positive integer representative of a number of columns, each of the two-column pairs of Mx1 memory cells comprises a first column of Mx1 one-bit memory cells and a second column of Mx1 one-bit memory cells. The first group of I / O pins, which correspond to the first column of Mx1 one-bit memory cells, are on a first side of the layout of the array and the second group of I / O pins, which correspond to the second column of Mx1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

Description

technical field [0001] The present invention relates generally to integrated circuit layouts for memory circuits, and more particularly, to double-pitch layout techniques in designing memory circuit layouts. Background technique [0002] Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims presented and are not admitted to be prior art by inclusion in this section. [0003] Memory circuitry is a key component, but it typically occupies a relatively large area and tends to dissipate large amounts of power in most integrated circuit technologies. A common storage circuit, such as a static random access memory (SRAM), includes a word-line (word-line) driver circuit, a control circuit, an input / output (I / O) circuit, and a one-bit storage unit (one- bit memory cell) array. The I / O circuit generally includes an I / O pin, a sense amplifier (sense amplifier, SA) and a pre-charging circuit. The I / O pins include a data input (da...

AI Technical Summary

Problems solved by technology

However, the small pitch of the I / O pins of the I / O circuit can make placement or routing of the I / O pins to other circuits more difficult

In the layout of the memory circuit, the small spacing of the I / O pins of the I / O circuit also causes a large load capacitance, which reduces the read / write speed of the memory circuit

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