Semiconductor device, method for making the same, and chip

Abstract

The present invention provides a semiconductor device, a method for manufacturing the same, and a chip, including: providing a first wafer, forming a metal silicide layer on the surface of part of the first substrate; forming through-silicon vias and openings, the openings penetrating the metal A silicide layer and a partial thickness of the first dielectric layer expose the first metal layer; and a pad is formed, and the pad is formed in the through-silicon via and is electrically connected to the first metal layer. In the present invention, the metal silicide layer is used as the etching stop layer of the through-silicon hole, and the metal silicide layer and the first substrate have a higher etching selectivity ratio, which can enhance the etching of the first substrate in the process of forming the through-silicon hole. In order to avoid the incomplete etching of the first substrate resulting in poor contact between the final pad and the first metal layer or even open circuit; the opening process of the present invention only involves the metal silicide layer and the first dielectric layer. Compared with the traditional structure, the metal The thickness of the silicide layer has better uniformity, so that the process is better controlled, and damage to the first metal layer is effectively avoided.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor device and a manufacturing method thereof. Background technique [0002] TSV (Through Silicon Via) technology is a technology that realizes interconnection between chips by fabricating vertical conduction between chips and between wafers, which can make the stacking density higher in three dimensions. big. Three-dimensional chips allow for multi-layer stacking, enabling vertical stacking of multiple planar devices. In the wafer-level three-dimensional stacking technology, the backside lead process is an important technical link, that is, the electrical signal of the metal layer in the wafer is drawn out to the top of the wafer through the bonding pad. [0003] At present, the backside lead process is often realized by TSV (through silicon via) technology. The lead method of the backside pad has a small process window, and it ...

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Problems solved by technology

[0003] At present, the backside lead process is often realized by TSV (Through Silicon Via) technology. The lead method of the backside pad has a small process window, and it is easy to cause poor contact between the pad and the metal layer or even open the circuit in the silicon substrate area where the silicon substrate is too thick. The bottom area is too thin to easily cause serious damage to the metal layer

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