Semiconductor device and manufacturing method thereof and chip
A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as poor contact between pads and metal layers, damage to metal layers, and small process windows, to achieve The effects of better process control, good uniformity, and high etching selectivity ratio
Active Publication Date: 2021-10-01
WUHAN XINXIN SEMICON MFG CO LTD
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Problems solved by technology
[0003] At present, the backside lead process is often realized by TSV (Through Silicon Via) technology. The lead method of the backside pad has a small process window, and it is easy to cause poor contact between the pad and the metal layer or even open the circuit in the silicon substrate area where the silicon substrate is too thick. The bottom area is too thin to easily cause serious damage to the metal layer
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[0049] As mentioned in the background technology, the lead method of the back pad has a small process window, which may easily lead to poor contact between the pad and the metal layer or even open circuit in the area where the silicon substrate is too thick, and may cause damage to the metal layer in the area where the silicon substrate is too thin serious problem. The specific analysis is as follows:
[0050] Such as figure 1 As shown, after the upper wafer 10 and the lower wafer 20 are bonded, through-silicon vias V are formed by etching the substrate 11 of the upper wafer 10 1 , TSV V 1 It can stop on the STI (Shallow Trench Isolation) 12; then, form the opening V to open the STI 12 and the dielectric layer 14 2 , the opening V 2 The metal layer 15 is exposed; then in the opening V2 and TSV V 1 The welding pad 13 is formed in the middle, and the welding pad 13 is electrically connected with the metal layer 15, and the welding pad 13 leads the electrical signal of the m...
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and a chip. The method comprises the steps: providing a first wafer, and forming a metal silicide layer on the surface of a part of a first substrate; forming a silicon through hole and an open hole, wherein the open hole penetrates through the metal silicide layer and a part of thickness of the first dielectric layer and exposes a first metal layer; and forming a bonding pad, wherein the bonding pad is formed in the silicon through hole and is electrically connected with the first metal layer. According to the invention, a metal silicide layer is used as an etching stop layer of a silicon through hole, and the metal silicide layer and a first substrate have a higher etching selection ratio, so that the etching amount of the first substrate in a silicon through hole forming process can be enhanced, and poor contact and even open circuit between a final bonding pad and the first metal layer caused by incomplete etching of the first substrate can be avoided; and the hole forming process only relates to the metal silicide layer and the first dielectric layer, and compared with a traditional structure, the thickness of the metal silicide layer has better uniformity, so that the process is better controlled, and the first metal layer is effectively prevented from being damaged.
Description
technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor device and a manufacturing method thereof. Background technique [0002] TSV (Through Silicon Via) technology is a technology that realizes the interconnection between chips by creating vertical conduction between chips and between wafers, which can make the stacking density higher in three dimensions. Big. Three-dimensional chips allow multilayer stacking, enabling vertical stacking of multiple planar devices. In the wafer-level three-dimensional stacking technology, the back lead process is an important technical link, that is, the electrical signal of the metal layer in the wafer is led out to the top of the wafer through the pad. [0003] At present, the backside lead process is often realized by TSV (Through Silicon Via) technology. The lead method of the backside pad has a small process window, and it is easy to cause p...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L23/48H01L23/488H01L21/48
CPCH01L23/481H01L23/488H01L21/486
Inventor 朱奎薛广杰
Owner WUHAN XINXIN SEMICON MFG CO LTD