In-memory computing circuit chip based on magnetic cache and computing device

By adopting an in-memory computing circuit based on magnetic cache in the deep learning in-memory computing architecture and using a timer to set the data retention time, the problems of limited SRAM capacity and high MRAM write power consumption are solved, and efficient in-memory computing is achieved. Data storage and energy efficiency improvements.

CN113539318AActive Publication Date: 2021-10-22NANJING HOUMO TECH CO LTD
9 Cites 7 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2021-07-16
Publication Date
2021-10-22

AI Technical Summary

Technical Problem

In the existing deep learning in-memory computing architecture, SRAM-based cache capacity is limited and static power consumption is high, which affects energy efficiency; while MRAM-based storage weight data has long write delays and high write power consumption, making it difficult to meet the in-memory requirements. Computationally efficient requirements.

Method used

An in-memory computing circuit based on magnetic cache is used, and the data retention time of the magnetic cache unit is set through a timer. The high density and capacity of the magnetic cache unit are used to cache the data output by the in-memory computing unit, and based on the data volume and Throughput rate adjusts hold time to reduce write latency and power consumption.

Benefits of technology

It effectively improves the data storage capacity and energy efficiency of in-memory computing, overcomes the high power consumption defect of long write delays in magnetic cache units, and achieves high-capacity cache with lower power consumption, which is suitable for different in-memory computing scenarios.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The embodiment of the invention discloses an in-memory computing circuit based on a magnetic cache, and the circuit comprises at least one magnetic cache unit, at least one in-memory computing unit, and a timer. The magnetic cache unit in the at least one magnetic cache unit is used for caching data output by the corresponding in-memory computing unit as to-be-processed data within the corresponding data retention time; the timer is used for respectively setting data retention time for the at least one magnetic cache unit; and the in-memory computing unit in the at least one in-memory computing unit is used for extracting the data to be processed from the corresponding magnetic cache unit for calculation and outputting the computed data to other magnetic cache units. According to the embodiment of the invention, the invention achieves the flexible adjustment of the data retention time of the magnetic cache unit in various in-memory calculation scenes, and achieves the provision of a high-capacity cache for the data needed by in-memory computing under the lower power consumption.
Need to check novelty before this filing date? Find Prior Art

Citation Information

Patent Citations

  • Nonvolatile in-memory computing chip and operation control method thereof

    CN110597555A

  • Memory device and system, and manufacturing method of integrated circuit

    CN110659224A

  • Magnetic random access memory with error correction and compression circuit

    CN110660421A

  • Cache system used in cooperation with an error correction magnetic random access memory

    CN110660422A

  • Time domain in-memory computing array structure based on magnetic random access memory

    CN112581996A

Cited By

  • In-memory computation pipeline multiplication and addition circuit supporting internal data updating

    CN115312095A

  • An in-memory computation pipelined multiply-accumulate circuit that supports internal data updates

    CN115312095B

  • Data transmission device and method suitable for storage and calculation integrated chip

    CN115665268A

  • A data transmission device and method suitable for in-memory computing chips

    CN115665268B

  • Non-volatile hybrid memory circuit and method supporting cache management

    CN118331896A