Photoelectric integrated circuit for message compression in message hash algorithm

A technology of integrated circuits and hashing algorithms, applied in optical computing equipment, neural learning methods, biological neural network models, etc. Energy efficiency, improved computing performance, low power consumption

Active Publication Date: 2021-11-12
TSINGHUA UNIV
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Problems solved by technology

[0005] This application provides an optoelectronic integrated circuit for message compression in message hashing algorithm to solve the problem of large power consumption during each round of dynamic flipping of message hashing algorithm based on simple circuits in the related art, resulting in power consumption during message compression Large, reducing computing performance and other issues

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  • Photoelectric integrated circuit for message compression in message hash algorithm
  • Photoelectric integrated circuit for message compression in message hash algorithm
  • Photoelectric integrated circuit for message compression in message hash algorithm

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Embodiment Construction

[0025] Embodiments of the present application are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary, and are intended to explain the present application, and should not be construed as limiting the present application.

[0026] Most of the traditional secure hash algorithms are implemented by software, and there is a risk that the intermediate value may be intercepted, resulting in the possibility that the plaintext may be reversed, and the calculation rate of the software is low. These shortcomings can be overcome by hardware circuit ASIC and GPU, but as Moore's Law slows down or even comes to an end, hardware circuits based on traditional integrated circuit technology are facing bottlenecks in performance and energy efficiency. Optoelectro...

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Abstract

The invention relates to the technical field of electrical digital data processing, in particular to a photoelectric integrated circuit for message compression in a message hash algorithm. The photoelectric integrated circuit is provided with first to Nth levels of optical neural networks and a photoelectric detector array in an integrated manner. The first to Nth levels of optical neural networks are used for carrying out message compression operation in a message hash algorithm on multiple paths of initial optical signals which are input in parallel through the waveguide step by step from the first to Nth levels, carrying out message compression operation on messages loaded to the multiple paths of initial optical signals through each level of optical neural network, and carrying out step-by-step compression to obtain final optical signals meeting compression conditions; and the photoelectric detector array is used for converting the final optical signal into an electric signal for carrying a message compression result. Therefore, the problems of high power consumption during message compression, reduction of operation performance and the like caused by high power consumption of dynamic flipping during implementation of each round of operation of a message hash algorithm based on a hardware circuit in related technologies are solved.

Description

technical field [0001] This application relates to the technical field of electrical digital data processing, in particular to an optoelectronic integrated circuit used for message compression in message hash algorithm. Background technique [0002] The message hash algorithm can also be called SHA (Secure Hash Algorithm, secure hash algorithm), which can calculate a fixed-length message digest corresponding to a digital message, and is often used in digital signatures and data integrity checks. [0003] Since the message hash algorithm is usually implemented by software, there is a risk that the intermediate value may be intercepted, and the plaintext may be reversed. At the same time, the calculation rate of the software is low. Therefore, in related technologies, hardware circuits such as ASIC (Application Specific Integrated Circuit, application-specific integrated circuit) and GPU (Graphics Processing Unit, graphics processing unit), etc. to implement the operation of t...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06E3/00G06N3/067G06N3/08
CPCG06E3/005G06N3/0675G06N3/08
Inventor 戴琼海邓辰辰郑纪元吴嘉敏
Owner TSINGHUA UNIV
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