Write-in method of flash memory array

Abstract

The invention provides a write-in method of a flash memory array. The flash memory array comprises: a plurality of flash memory units arranged along a row direction and a column direction; a plurality of word line groups extending in a row direction; and a plurality of bit line groups extending in the column direction. A flash memory unit pair is arranged at the intersection point of the word line group and the bit line group and comprises a first flash memory unit and a second flash memory unit which are adjacent in the row direction and share the same bit line group. The write-in method includes applying each writing voltage to a first electrode and a second electrode of a selected flash memory cell and a gate electrode of a memory transistor, wherein the writing voltage applied to an electrode connected to the written memory transistor is higher than an electron barrier height at an interface between the substrate and a gate dielectric stack of the memory transistor. The write-in method of the flash memory array has the advantages of being low in operation power consumption and high in programming speed, and the number of flash memory units written in parallel is increased, so the data writing throughput rate of the memory is increased.

Description

technical field [0001] The present disclosure relates to the field of semiconductor technology, and in particular, the present disclosure relates to a writing method of a flash memory array. Background technique [0002] Flash memory, referred to as flash memory, is a non-volatile memory, that is, the stored data will not be lost even if the power is cut off, and it is especially suitable for mobile communication and computer storage components and other fields. In addition, some flash memories also have high-density storage capabilities, and are suitable for applications such as large-capacity mobile storage media. [0003] Conventional flash memory adopts a floating gate cell structure. The floating gate non-volatile memory originated from the MIMIS (Metal-Insulator-Metal-Insulator-Semiconductor: Metal-Insulator-Metal-Insulator-Semiconductor) structure proposed by D.Kahng and S.Sze in 1967. This structure adds a metal floating gate and an ultra-thin tunnel oxide layer on...

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Problems solved by technology

[0004] However, the floating gate flash memory has the following disadvantages: the process is relatively complicated; the vertical height of the gate structure is increased due to the existence of the floating gate structure in the flash memory unit, which is not conducive to scaling down the process size and cell area; Conductivity, the stored charge can move freely in the floating gate, which is not conducive to improving the reliability of the memory

However, the source lines of existing flash memory arrays are formed in the active area, and the sheet resistance of the active area is much higher than that of metal

Therefore, in order to reduce the series resistance of the source lines, it is necessary to short-circuit the source lines in the active area through metal common source lines every few rows or columns in the row or column direction, resulting in an increase in the area overhead of the flash memory array.

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