Capacitance mismatch calibration method and system for successive approximation type analog-to-digital converter

Abstract

The invention provides a capacitance mismatch calibration method and system for a successive approximation type analog-to-digital converter. The capacitance mismatch calibration method specifically comprises the following steps: S1, inputting a digital random jitter signal and an analog input signal into a capacitance type digital-to-analog converter together; S2, comparing the output of the capacitive digital-to-analog converter with a reference point through a comparator, and storing the obtained output digital code; S3, calculating an evaluation value of the corresponding output digital code; S4, obtaining a correlation coefficient according to the evaluation value and the digital random jitter signal, if the absolute value of the correlation coefficient is close to 0 in an error allowable range, obtaining a correct capacitance weight, otherwise, carrying out feedback adjustment on the capacitance weight, and returning to the step S3; and S5, obtaining an ideal code by compensating the digital code, and updating the digital code. Through injection and digital calibration of the pseudo-random signal in the analog signal domain, a value closer to the actual weight of the capacitor array is obtained, so that dynamic parameters such as the signal-to-noise distortion ratio of the circuit are improved.

Description

technical field [0001] The invention relates to the field of mixed signal circuits, in particular to a capacitance mismatch calibration method and system for a successive approximation analog-to-digital converter. Background technique [0002] In the communication circuit, the analog-to-digital converter (ADC) is a very important module, which is responsible for converting the analog signal received by the radio frequency front end (RFFE) into a digital signal and providing it to the digital processor (DSP) for processing. In the development process of the receiver architecture, due to the increasingly simplified design of the RF front-end and the faster and more powerful digital processor functions, the performance of the ADC has increasingly become a bottleneck restricting the performance of the receiver. The indicators to measure the analog-to-digital converter mainly include bandwidth (speed), precision and power consumption. [0003] The successive approximation (SAR) ...

AI Technical Summary

Problems solved by technology

In the actual production process of the chip, the matching degree of these devices is affected by many factors, such as process matching parameters, device area and layout design, etc., so that the matching of the capacitor array often cannot achieve the preset goal

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