MOSFET device and preparation method thereof

Abstract

The invention discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method, and relates to the field of semiconductor power devices. The anti-static and anti-impact capabilities of the grid electrode can be effectively enhanced, and the purpose of withstand voltage of the device is achieved by using the ESD polycrystalline silicon layer as a mask plate to block the injection of the P-type body region at the periphery. The method comprises the steps that active region grooves are formed in a first conduction type drift layer, a second layer of first conduction type source regions are arranged between the active region grooves and on one sides of the active region grooves, and the active region grooves are located in an MOSFET region; a first layer of second conductive type body region is arranged on the non-doped polycrystalline silicon layer in the MOSFET region; the non-doped polycrystalline silicon layer is arranged above the first conductive type drift layer; a first layer of second conductive type body region and a first layer of first conductive type source region are arranged on the non-doped polycrystalline silicon layer in the ESD region; a first layer of second conductive type body region is arranged on the non-doped polycrystalline silicon layer in the Rg region; and a second layer of second conductive type body region is arranged in the first conductive type drift layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor power devices, in particular to a MOSFET device and a preparation method. Background technique [0002] For power devices MOSFE (English: Metal-Oxide-Semiconductor Field-Effect Transistor, Chinese: Metal-Oxide-Semiconductor Field-Effect Transistor) devices, in order to pursue lower internal resistance in some application fields, mainly by reducing each key size The width of the device can be achieved by increasing the device cell density, but the reduction of the critical size of the device will inevitably compress the thickness of the gate oxide layer, thereby reducing the antistatic and impact resistance of the device gate. Contents of the invention [0003] The embodiment of the present invention provides a MOSFET device and a preparation method, which can effectively enhance the antistatic and impact resistance of the gate, and use the ESD polysilicon layer as a mask to block the impla...

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Problems solved by technology

[0002] For power devices MOSFE (English: Metal-Oxide-Semiconductor Field-Effect Transistor, Chinese: Metal-Oxide-Semiconductor Field-Effect Transistor) devices, in order to pursue lower internal resistance in some application fields, mainly by reducing each key siz...

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