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49results about How to "Reduce gate current" patented technology

Side wall etching method for reducing heat current carrier injection damage

The invention discloses a side wall etching method for reducing heat current carrier injection damage. Ion injection is carried out on a side wall deposition layer by using neutral ions, and the ion injection direction forms an included angle with the direction vertical to a substrate and is inclined towards the source electrode direction, so the etching speed on the side wall above a source electrode region is higher than the etching speed on the side wall above a drain electrode region in the side wall etching process, after etching, the cross section width of the side wall of a source electrode is relatively reduced, and the cross section width of the side wall of a drain electrode is relatively increased. After voltage is applied on a grid electrode, the intensity of a longitudinal electric field generated at the drain terminal is weakened, so electron hole pairs are generated through the collision of current carriers accelerated by a transverse electric field, and the injection into the grid electrode can be realized by holes under the effect of the weak longitudinal electric field, so the grid current formed because of the hot current carrier injection is reduced, and the hot current carrier injection damage of a semiconductor device is reduced.
Owner:SHANGHAI HUALI MICROELECTRONICS CORP

Flat-panel display device with branched side-bottom gate modulation structure and its preparing process

The invention relates to a flat-panel display of a forked side bottom grid-controlled structure and the making process thereof, comprising: sealed vacuum cavity composed of anode glass panel, cathode glass panel, and peripheral glass frame; anode conducting layer on the anode glass panel and fluorescent powder layer prepared on the anode conducting layer; supporting wall structure and degassing agent auxiliary component between the anode glass panel and cathode glass panel; and grid lead layer, carbon nanotube and forked side bottom grid-controlled structure on the cathode glass panel; and it can further increase operating current of anode and reduce operating voltage of grid structure, and has advantages of stable and reliable making course, simple making process, low making cost, and simple structure.
Owner:ZHONGYUAN ENGINEERING COLLEGE

Preparation method of mica film and transistor

The invention discloses a preparation method of a mica film. The method comprises that a substrate is placed in a vacuum pulse laser deposition device; and a mica target material is corroded by pulse laser so that the surface of the mica target material generates a plasma plume, and the plasma plume deposed on the substrate grows to form the uniform mica film. The invention also discloses a transistor which includes the mica film prepared by the preparation method. The mica film is introduced into the transistor and serves as a dielectric layer, and a layered 2D nano structure of mica is ultrathin, and is conducive to grid modulation of the transistor and high-density integration of the transistor in the vertical direction. In addition, the surface of the mica film is very smooth, carriers of the transistor can be avoided from influence of surface roughness and a trapping state, and the transistor can obtain a higher carrier mobility rate.
Owner:SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI

MOSFET device and preparation method thereof

The invention discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method, and relates to the field of semiconductor power devices. The anti-static and anti-impact capabilities of the grid electrode can be effectively enhanced, and the purpose of withstand voltage of the device is achieved by using the ESD polycrystalline silicon layer as a mask plate to block the injection of the P-type body region at the periphery. The method comprises the steps that active region grooves are formed in a first conduction type drift layer, a second layer of first conduction type source regions are arranged between the active region grooves and on one sides of the active region grooves, and the active region grooves are located in an MOSFET region; a first layer of second conductive type body region is arranged on the non-doped polycrystalline silicon layer in the MOSFET region; the non-doped polycrystalline silicon layer is arranged above the first conductive type drift layer; a first layer of second conductive type body region and a first layer of first conductive type source region are arranged on the non-doped polycrystalline silicon layer in the ESD region; a first layer of second conductive type body region is arranged on the non-doped polycrystalline silicon layer in the Rg region; and a second layer of second conductive type body region is arranged in the first conductive type drift layer.
Owner:华羿微电子股份有限公司

Flat-panel display device with ring-gate modulated valley cathode structure and its preparing process

The invention relates to a flat-panel display of an annular grid-controlled valley mouth-type cathode structure and the making process thereof, comprising: sealed vacuum cavity composed of anode glass panel, cathode glass panel, and peripheral glass frame; anode conducting layer on the anode glass panel and fluorescent powder layer prepared on the anode conducting layer; supporting wall structure and degassing agent auxiliary component between the anode glass panel and cathode glass panel; and grid lead layer, carbon nanotube and annular grid-controlled valley mouth-type cathode structure on the cathode glass panel; and it can further improve whole displayed image quality and reduce operating voltage of grid, and has advantages of stable and reliable making course, simple making process, low making cost, and simple structure.
Owner:ZHONGYUAN ENGINEERING COLLEGE
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