Array substrate, preparation method thereof and display device

Abstract

The invention discloses an array substrate, a preparation method thereof and a display device. The preparation method comprises the steps: sequentially forming a low-temperature polycrystalline silicon active layer, a grid insulating layer, a grid structure layer and an interlayer insulating layer on the substrate, wherein the grid structure layer comprises a grid and a grid line which are arranged on the same layer; sequentially forming a first semiconductor material layer and a photoresist pattern on one side, far away from the substrate, of the interlayer insulating layer, wherein the photoresist pattern corresponds to a source electrode, a drain electrode and a data line to be formed; etching the photoresist pattern and the first semiconductor material layer to form a source electrode, a drain electrode and a data line; sequentially forming a flat layer, a pixel defining layer and a light emitting device layer on the sides, away from the substrate, of the source electrode, the drain electrode and the data line, wherein a groove is formed in the side, back on to the substrate, of the grid line, an overlapping area exists between the orthographic projection of the grid line on the substrate and the orthographic projection of the data line on the substrate, and the overlapping area is located in the orthographic projection area of the groove on the substrate.

Description

technical field [0001] The present invention generally relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display device. Background technique [0002] In display devices, especially in LTPS (Low Temperature Poly-silicon, low-temperature polysilicon) products, there are inevitably crossing metal driving lines (such as gate lines and data lines) in various regions, among which the Top Gate (top gate) structure is the research and development a key direction. [0003] In the existing Top Gate structure, the gate insulating layer (GI) covers the gate metal layer (Gate) including the gate and the gate line to reduce the influence of the short channel effect, and the edge of the GI is more than the edge of the Gate The part of the gate insulating layer (GITail) is the gate insulating layer tail (GITail). When the subsequent interlayer dielectric layer (ILD) is formed, the ILD needs to complete two consecutive ...

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Problems solved by technology

[0003] In the existing Top Gate structure, the gate insulating layer (GI) covers the gate metal layer (Gate) including the gate and the gate line to reduce the influence of the short channel effect, and the edge of the GI is more than the edge of the Gate The part of the gate insulating layer (GITail) is the gate insulating layer tail (GITail). When the subsequent interlayer dielectric layer (ILD) is formed, the ILD needs to complete two consecutive climbing slopes (GI slope and Gate slope) at the GI Tail position, which is prone to wrinkles. After the metal layer is deposited, a similar tip phenomenon is formed at the aforementioned climbing point, and the thickness of the ILD at the climbing point is relatively thin. In addition, when forming the data lines on the same layer as the source and drain metal layer, it is easy to overcut the ILD.

If an electrostatic effect occurs, DGS (Data-Gate Short, gate line and data line short circuit) is prone to occur at the position where the metal traces cross, thereby reducing the yield rate of the display panel process

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