Self-acceleration locking phase-locked loop

Abstract

The invention discloses a self-acceleration locking phase-locked loop, and the phase-locked loop comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a frequency divider, a rectifier, a filter and a bandwidth control circuit. The phase frequency detector, the charge pump, the low-pass filter and the voltage-controlled oscillator are sequentially connected; the output of the voltage-controlled oscillator is fed back to one input end of the phase frequency detector through the frequency divider, and the other input end of the phase frequency detector is connected with the reference frequency source. The output end of the phase frequency detector is further connected with the input end of the rectifier, the rectifier, the filter and the bandwidth control circuit are sequentially connected, and the bandwidth control circuit is used for generating a control word signal in proportional relation with an output signal of the phase frequency detector and inputting the control word signal to the low-pass filter; the bandwidth is controlled by controlling the access number of capacitors in the parallel capacitor array of the low-pass filter, so that the phase-locked loop accelerates to lock the reference frequency.

Description

technical field [0001] The invention relates to a phase-locked loop structure. Background technique [0002] With the continuous improvement of the performance of integrated circuits, the frequency of the chip is also gradually increasing, but due to the limitation of printed circuit board technology, it becomes more and more difficult to provide a higher frequency clock signal to the chip externally. Therefore, inside the chip, It is very important to generate a stable clock. Phase-locked loops (PLL) is a frequency and phase synchronization technology realized by feedback control principle. Its function is to synchronize the clock output by the circuit with its external reference clock. When the frequency or phase of the reference clock changes, the phase-locked loop detects the change and adjusts the output frequency through its internal feedback system until the two are resynchronized, also known as "phase-locked". In many application scenarios, the frequency required b...

AI Technical Summary

Problems solved by technology

In many application scenarios, the frequency required by integrated circuits is not single, and frequency hopping may be required according to needs. How to quickly lock after frequency hopping brings challenges to PLL design

Some circuits have complex application scenarios, and external interference will affect the frequency locking effect, causing the phase-locked loop to lose lock. Under the action of negative feedback adjustment, how to restore the locked frequency is also a difficult problem

[0003] In the prior art, there are methods that add more charging branches in the charge pump, which will cause additional power consumption and noise; there are methods that rely on digital assistance technology, and this method will cause more serious noise problems

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