Power semiconductor device and manufacturing method thereof

Abstract

The invention discloses a power semiconductor device and a manufacturing method thereof, the power semiconductor device comprises a silicon carbide N-type substrate, an N-type epitaxial layer is arranged on the silicon carbide N-type substrate, a P base region is arranged on the N-type epitaxial layer, an N + source region and a P + source region are formed in the P base region to form an intermediate device, and a P + source region is formed in the P base region. An insulating medium material layer and a gate medium material layer are deposited on the surface of the intermediate device, polycrystalline silicon is deposited on the insulating medium material layer and the gate medium material layer, ohmic contact layers are formed on the surfaces of the N + source region and the P + source region, and a Schottky contact layer is formed on the surface of the N-type epitaxial layer between the P + source region and the P + source region. Source electrodes are arranged on the ohmic contact layer and the Schottky contact layer, a grid electrode is arranged on the polycrystalline silicon, and a drain electrode is arranged on the back face of the silicon carbide N-type substrate. The anti-parallel diode has the advantages of reducing gate leakage charge, improving the chip utilization rate, reducing the loss of the anti-parallel diode, improving the surge capacity of the anti-parallel diode and the like.

Description

technical field [0001] The invention mainly relates to the technical field of semiconductors, in particular to a power semiconductor device and a manufacturing method thereof. Background technique [0002] Power MOSFET devices In switching applications, the gate charge must be overcome to regulate the transistor to a specific voltage, and the switching speed of the transistor decreases significantly at larger gate charges. In addition, transistors suffer from higher gate charges and increased failure rates. The gate-to-drain charge is a major part of the gate charge, and applying a switching voltage to the gate amplifies the gate-to-drain capacitance due to the Miller effect. Therefore, it is desirable to minimize gate-to-drain capacitance to reduce gate charge and improve transistor switching speed, efficiency, and failure rate. [0003] In power electronic systems, power MOSFET devices usually need to be used with free wheeling diodes (Free Wheeling Diode, FWD) to ensure...

AI Technical Summary

Problems solved by technology

Low channel mobility is the key factor for the large on-resistance of silicon carbide planar gate MOSFETs. At the same time, silicon carbide can only be implanted with ions. The N+ source region and P-type well PW of planar gate MOSFETs use two-layer photolithographic registration. , due to easy misalignment, the overlay deviation will cause the channel length of the two half-cells (eg figure 1 Shown in 31 and 32) is asymmetrical, causing the conduction current of the device to select the shorter channel to flow to the drain, and half of the cells of the longer channel are not used

[0005] In summary, the current power MOSFET devices have defects such as large gate-to-drain charge, low utilization rate of silicon carbide chips, and large loss of freewheeling diodes.

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