Chip packaging structure

Abstract

The invention provides a chip packaging structure. The chip packaging structure comprises a packaging substrate, wherein a first surface of the packaging substrate is electrically connected with a driving chip; a stress dispersion layer which is arranged on the first surface and located on the periphery of the driving chip, wherein the thickness of the stress dispersion layer is greater than or equal to the thickness of the driving chip in the direction perpendicular to the first surface; a stress buffer layer which covers the stress dispersion layer and wraps the driving chip; and a semiconductor chip group which is arranged on the stress buffer layer and is electrically connected with the first surface. By arranging the stress dispersion layer, the downward stress generated by the semiconductor chip set due to external force application in the packaging process can be dispersed, so the damage to a bottom chip in the semiconductor chip set due to the fact that stress is concentrated in an area, corresponding to the edge of the driving chip, in the stress buffer layer in the prior art is effectively avoided; therefore, the risk of short circuit caused by failure of the chip in the semiconductor chip set is reduced, and the performance of the chip packaging structure is improved.

Description

technical field [0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular, relates to a chip packaging structure. Background technique [0002] In the prior art, the main function of flash memory (Flash Memory) memory is to keep stored information for a long time without power on. It has the advantages of high integration, fast access speed, and easy erasing and rewriting. Widely used in electronic products. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), a three-dimensional NAND flash memory is further proposed. [0003] Packaging is an important step in the manufacturing process of 3D NAND memory. At present, the chip package structure is usually to electrically connect the chip set to the package substrate through wiring, and fix the package of the chip set through the package shell. However, chips in the prior art are prone to short cir...

AI Technical Summary

Problems solved by technology

[0004] The main purpose of the present application is to provide a chip packaging structure to solve the problem that chips in the prior art are prone to short circuits after packaging

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