Cleaning process for solving patterning collapse of advanced node

Abstract

The invention discloses a cleaning process for solving patterning collapse of an advanced node, and relates to the technical field of semiconductor manufacturing. The cleaning process comprises the operation steps of first-time chemical solution cleaning, first-time ultrapure water cleaning, drying and surface covering treatment, high-temperature isopropanol implantation covering, supercritical fluid implantation, isopropanol and supercritical fluid precipitation and the like. Isopropanol molecules carrying water molecules can be removed from the surface of the wafer, so that the stability of the surface property of the wafer treated by a wet process is controlled, and the phenomenon of tension drawing graphical collapse of the water molecules and the isopropanol molecules on the surface of the wafer is avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a cleaning process for solving pattern collapse of advanced nodes. Background technique [0002] The continuous advancement of wafer manufacturing technology involves the patterned structure of related nanoscale microstructures such as logic integrated circuits, storage, and micro-electromechanical systems. The size of the gate structure is continuously reduced, and the process node has changed from the popular 28nm Advance to below 5nm, on the relevant electronic channel structure on the semiconductor wafer, particles or other related pollutant residues will affect the production process, but in the various cleaning, etching, deglue, film removal, electroplating of the wafer , grinding or multiple, wet processes will face the issue of removing particles and pollutants. Traditional cleaning methods and drying processes are no longer effective. The manufacturin...

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Problems solved by technology

[0002] The continuous advancement of wafer manufacturing technology involves the patterned structure of related nanoscale microstructures such as logic integrated circuits, storage, and micro-electromechanical systems. The size of the gate structure is continuously reduced, and the process node has changed from the popular 28nm Advance to below 5nm, on the relevant electronic channel structure on the semiconductor wafer, particles or other related pollutant residues will affect the production process, but in various cleaning, etching, deglue, film removal and electroplating of the wafer , grinding or multiple, wet processes will face the issue of removing particles and pollutants. Traditional cleaning methods and drying processes are no longer effective. The manufacturing problems that tend to be nano-scale or even close to the picometer-scale structure, in the traditional The wet-related process of the current advanced node process faces the problem of collapse of the patterned structure due to tension problems

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