RapidIO low-delay and high-transmission-efficiency architecture implementation method and electronic equipment

Abstract

The invention provides a RapidIO low-delay and high-transmission-efficiency architecture implementation method, a physical layer, a transmission layer and a logic layer all adopt the same clock domain, a unified clock architecture is adopted, and cross-clock-domain modules are applied to the sending side and the receiving side of a physical coding sub-layer of the physical layer so as to achieve bridging of different clock domains. According to the RapidIO low-delay and high-transmission-efficiency architecture implementation method, normal transmission of data of different clock domains on the two sides of a traditional RapidIO controller can be achieved, due to the fact that the clock relation between part of modules is simplified, functional logic development and design are facilitated, more importantly, transmission delay caused in the redundant cross-clock operation process is removed, and the clock structure and the logic development of the RapidIO controller are greatly simplified.

Description

technical field [0001] The invention belongs to the technical field of RapidIO communication, and in particular relates to a RapidIO low-delay, high-transmission-efficiency framework realization method and electronic equipment. Background technique [0002] The traditional Xilinx RapidIO IP core adopts a typical three-layer architecture design, including: Logic Layer, Buffer Layer and Physical Layer. The logic layer module mainly realizes the definition of the upstream interface , header parsing and message format conversion; the cache module is mainly used to store and manage sending and receiving messages to achieve efficient data transmission; the physical layer module mainly completes port initialization, link initialization, message transmission, and control Symbol generation and parsing, IDLE message generation and parsing, and error management related content, such as figure 1 as shown, figure 1 The detailed structure and peripheral logic block diagram of the IP are...

AI Technical Summary

Problems solved by technology

[0009] like Figure 4 As shown, when the above RapidIO dual-end device A and device B send messages at the same time, since the priority of sending messages is higher than the priority of replying to the peer, when device B receives the message from device A, But at this time, the message that needs to be sent by the local end needs to be sent out first, and the response confirmation that needs to reply to device A cannot be sent out in time. After sending the message for a period of time, device A fails to receive the confirmation, so it pauses. Send the packet until the confirmation message from device B is received

Images