Semiconductor device and manufacturing method thereof

A semiconductor and device technology, applied in the field of semiconductor storage devices, can solve the problem that the test structure cannot accurately reflect the contact situation, and achieve the effect of improving test accuracy and product quality

Pending Publication Date: 2022-03-04
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The invention provides a semiconductor device and a manufacturing method thereof to solve the problem that the test structure in the current semiconductor device cannot accurately reflect the contact situation

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

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Embodiment Construction

[0037] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar improvements without departing from the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

[0038] It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or...

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PUM

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Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a semiconductor substrate, and the semiconductor substrate comprises a plurality of chip areas and cutting channels used for separating the chip areas; a test structure is formed in the cutting channel, the test structure comprises an active region and a connecting structure, the active region is formed in the semiconductor substrate, the connecting structure is located at the end part of the active region, and the plurality of active regions located on the same column are sequentially connected end to end through the connecting structure; the test structure is used for bit line contact resistance test. In the embodiment of the invention, the semiconductor device is provided with a test structure for testing the bit line contact resistance in a cutting channel, and a plurality of active regions in the same column are sequentially connected end to end through a connection structure at the end part of the active region, so that the sum of the contact resistance of a plurality of bit lines in the same column and the resistance value of the active regions is obtained; the problem that measurement is inaccurate due to the fact that the shallow trench isolation structure is abnormal is solved, the testing accuracy is improved, and then the product quality is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor storage devices, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] With the shrinking of the size of semiconductor devices, the 17nm Dynamic Random Access Memory (DRAM) process is equivalent to the 19nm DRAM, the size of the transistors in the memory cell array area and the peripheral circuit area is getting smaller and smaller, and the process is complicated In order to monitor the manufacturing process of semiconductor devices to ensure the reliability of semiconductor devices, the usual practice is to form a test structure (testkey) in semiconductor devices for testing and testing of some key parameters of semiconductor devices. Simulation to ensure the quality of semiconductor devices shipped. [0003] The test of the key parameters of the semiconductor device includes the test of the resistance of the semiconductor device and the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66H01L27/108H01L21/8242
CPCH01L22/32H01L22/14H10B12/01H10B12/00H01L22/00
Inventor 黄晨蔡孟峯
Owner CHANGXIN MEMORY TECH INC
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