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Formation method of semiconductor structure

A semiconductor and conductive structure technology, applied in the field of semiconductor structure formation, can solve the problems such as semiconductor structure performance needs to be improved, and achieve the effect of reducing the difficulty of etching process, low process difficulty and improving performance

Pending Publication Date: 2022-03-04
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the performance of semiconductor structures formed in the prior art still needs to be improved

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Experimental program
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Embodiment Construction

[0028] It should be noted that "surface", "upper", for describing the relative positional relationship of the space, is not limited to whether or not it is directly in contact.

[0029] First, the reason for the performance of existing semiconductor structures is detailed in connection with the accompanying drawings. Figure 1 to 2 It is a schematic structural diagram of the formation method of existing semiconductor structures.

[0030] Please refer to figure 1 Provide substrate 100, the substrate 100 having a first dielectric layer 120 and a plurality of gate structures 110 having a source leak-doped region 130 on the substrate 100 on both sides of the gate structure 110, and the source can be drained. The surface of the region 130 has a plug 140, the first dielectric layer 120 located at the gate structure 110 and the source leak-doped region 130 and the plug surface 140; forming a second dielectric layer 150 on the surface of the first dielectric layer 120 .

[0031] Please ref...

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Abstract

A method for forming a semiconductor structure comprises the following steps: forming a second dielectric layer on the surface of a first dielectric layer, the top surface of a gate structure and the top surface of a plug; forming a first opening exposing the surface of the first dielectric layer in the second dielectric layer, wherein the first opening exposes the top surfaces of the at least two gate structures or the top surfaces of the at least two plugs; forming a first initial conductive structure in the first opening; part of the first initial conductive structure is etched until the surface of the first dielectric layer is exposed, discrete first conductive structures are formed, and the first conductive structures are located on the top surface of the gate structure or the top surface of the plug. The first initial conductive structures are large in size in the direction perpendicular to the extension direction of the gate structure, the difficulty of the etching process for forming the first initial conductive structures is reduced, the second openings ensure that the adjacent first conductive structures can be isolated, and a process window is increased.

Description

Technical field [0001] The present invention relates to the field of semiconductor manufacturing techniques, and more particularly to a method of forming a semiconductor structure. Background technique [0002] With the continuous development of integrated circuit manufacturing technologies, people's requirements for integrated circuits become higher and higher. In order to improve integration, reduce cost, the key size of the component is constantly smaller, the circuit density inside the integrated circuit is increasing, which makes the wafer surface unable to provide sufficient area to make the required interconnect. [0003] The connection plug within the transistor structure includes a connection plug located on the gate structure surface for connecting the gate structure and an external circuit; and a connection plug located on the surface of the source leak-doped region for realizing the transistor source region or The drain area is connected to the external circuit. In or...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
CPCH01L21/76807H01L21/76831H01L21/76852H01L21/76879
Inventor 赵炳贵
Owner SEMICON MFG INT (SHANGHAI) CORP