BPSK modulated UWB transmitter radio frequency front-end chip architecture

A radio frequency front-end and transmitter technology, which is applied in the field of architecture design of UWB transmitter radio frequency front-end chips, can solve problems such as complexity and unsuitability to standard protocols and architectures, and achieve the effect of reducing power consumption and chip power consumption

Pending Publication Date: 2022-03-15
河南省联睿智能科技研究院有限公司
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AI-Extracted Technical Summary

Problems solved by technology

[0006] In order to solve the defect that the existing UWB transmitter radio frequency front end is not suitable for the standard protocol...
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Abstract

The invention discloses a BPSK (binary phase shift keying) modulated UWB (ultra wide band) transmitter radio frequency front-end chip architecture which comprises an ultra wide band pulse generator, a pulse shaper, a first balun, an intermediate frequency amplifier, a second balun, a BPSK modulator, a PLL (phase locked loop) module, a small signal amplifier and a variable gain amplifier. The ultra-wideband pulse generator, the pulse shaper, the first balun, the intermediate frequency amplifier, the second balun and the BPSK modulator are connected in sequence to form a first access used for inputting baseband signals. The PLL module, the small signal amplifier and the BPSK modulator are connected in sequence to form a path II for inputting the clock frequency of the off-chip crystal oscillator; the BPSK modulator integrates and converts a baseband signal and the clock frequency into a UWB signal, and the UWB signal is output after the transmitting power of the output UWB signal is adjusted through the variable gain amplifier; and the power supply management module is used for converting power supply voltage of an external power supply into working voltage required by a module circuit in the chip.

Application Domain

Phase-modulated carrier systems

Technology Topic

Radio frequencyBalun +23

Image

  • BPSK modulated UWB transmitter radio frequency front-end chip architecture
  • BPSK modulated UWB transmitter radio frequency front-end chip architecture
  • BPSK modulated UWB transmitter radio frequency front-end chip architecture

Examples

  • Experimental program(1)

Example Embodiment

[0042] In order to facilitate the understanding and implementation of the present invention by those of ordinary skill in the art, the present invention will be further described in detail below with reference to the accompanying drawings and implementation examples. Inventions, general replacements well known to those skilled in the art are also covered within the protection scope of the present invention.
[0043] like figure 1 As shown, the BPSK modulated UWB transmitter RF front-end chip architecture includes: an ultra-wideband pulse generator 11, a pulse shaper 12, a balun 13, an intermediate frequency amplifier 14, a balun 2 15, a BPSK modulator 18, and a PLL module 16. Small signal amplifier 17 and variable gain amplifier 19;
[0044] The UWB pulse generator 11, the pulse shaper 12, the balun one 13, the intermediate frequency amplifier 14, the balun two 15, and the BPSK modulator 18 are sequentially connected to form a path one, which is used to input the baseband signal DATA;
[0045] The PLL module 16, the small-signal amplifier 17, and the BPSK modulator 18 are sequentially connected to form a second path, which is used to input the clock frequency of the off-chip crystal oscillator;
[0046] The BPSK modulator 18 integrates and converts the baseband signal DATA and the clock frequency into a UWB signal, and then outputs the UWB signal after adjusting the transmit power of the output UWB signal through the variable gain amplifier 19;
[0047] The BPSK-modulated UWB transmitter RF front-end chip architecture further includes a power management module 110 for converting the external power supply voltage Vdd into a working voltage required by a module circuit in the chip;
[0048] Wherein, the ultra-wideband pulse generator 11 is used to convert the input baseband signal DATA into a rectangular narrow pulse with a pulse width of about 2ns;
[0049] The input end of the pulse shaper 12 is connected with the output end of the ultra-wideband pulse generator 11, and is used to transform the rectangular narrow pulse with a pulse width of about 2ns into a Gaussian bell pulse with a root time of about 2ns;
[0050] The differential input end of the balun-13 is connected with the output end of the pulse shaper 12, and is used for converting the Gaussian bell-shaped pulse differential signal into a single-ended signal;
[0051] The input end of the intermediate frequency amplifier 14 is connected to the single-ended port of the balun-13 for amplifying the level amplitude of the Gaussian bell pulse;
[0052] The single-ended port of the balun 2 15 is connected to the output end of the intermediate frequency amplifier 14, and is used to convert the amplified Gaussian bell pulse into a differential signal with equal amplitude and phase difference of 180°;
[0053] The PLL module 16 is used to convert the input clock of the off-chip crystal oscillator into a required radio frequency carrier;
[0054] The small-signal amplifier 17 is used to linearly amplify the radio frequency carrier to a suitable level, reduce the frequency conversion loss of the double-balanced mixer, and improve the efficiency;
[0055] The BPSK modulator 18 realizes BPSK modulation and up-conversion of Gaussian bell-shaped pulses to form a UWB signal to be radiated with a specific center frequency;
[0056] The variable gain amplifier 19 is used to adjust the transmit power of the output UWB signal to comply with the radiated power spectral density specified by the radio regulations.
[0057] like figure 2 As shown, the ultra-wideband pulse generator 11 is the core of the whole chip architecture, and is used to generate a rectangular narrow pulse of 2ns. The ultra-wideband pulse generator 11 includes a time delay tuning circuit and a narrow pulse generator; the time delay tuning circuit is connected with the narrow pulse generator, and is used to convert the baseband signal DATA into a rectangular narrow pulse and output; The pulse generator 11 includes a DATA_N path and a DATA_P path, the DATA_P path is formed by connecting a time delay tuning circuit one 22 and a narrow pulse generator one 24, and the DATA_N path is formed by a first inverter (CMOS inverter) 21, The second time delay tuning circuit 23 and the narrow pulse generator two 25 are connected in turn to form; after the baseband signal DATA is connected to the UWB pulse generator 11, it is divided into two paths, and the first path is that the DATA_P path is connected to the time delay tuning circuit one 22 , the second path is the DATA_N path, the baseband signal DATA is converted into DATA* through the first inverter 21, and then connected to the second time delay tuning circuit 23; wherein the first inverter (CMOS inverter) in the second path The device) 21 converts the input baseband signal DATA into DATA*, ​​and then accesses the time delay tuning circuit 23; because the DATA and DATA* signals have the same amplitude, only the phase difference is 180°, the DATA and DATA* signals are processed by ultra-wideband After the pulse generator 11, it becomes the differential signals DATA_P and DATA_N.
[0058] like Figure 3A As shown, the delay tuning circuit one 22 and the delay tuning circuit two 23 both include a delay unit 32 and a reference unit 31, and both the delay unit 32 and the reference unit 31 include NMOS transistors and inverters, wherein the The delay unit 32 also includes a CTRL for controlling the delay. Specifically, the delay unit 32 is composed of a CMOS inverter 321, NMOS transistors 322 and 323, the source and drain of the NMOS transistor 323 are short-circuited and grounded to form a capacitor, and the gate of the NMOS transistor 322 is connected to the external control signal CTRL; the reference unit 31 is composed of a CMOS inverter 311, NMOS transistors 312 and 313, the source and drain of the NMOS transistor 313 are short-circuited and grounded to form a capacitor, and the gate of the NMOS transistor 312 is grounded. The input signal DATA is divided into two channels in the delay tuning circuit one 22 and the delay tuning circuit two 23, one is connected to the delay unit 32, and the other is connected to the reference unit 31. The gate voltages of the two circuit units are different, and two The NMOS tubes generate different source currents, resulting in different charging and discharging times of the two NMOS tubes, resulting in two signals DATA1 and DATA2 with different time delays. DATA1 lags DATA2 time Td, such as Figure 3B shown.
[0059] like Figure 4A As shown, the narrow pulse generator one 24 and the narrow pulse generator two 25 both include a first narrow pulse input terminal, a second narrow pulse input terminal, a second inverter 41, a NOR gate 42 and a narrow pulse output terminal; the first narrow pulse input terminal is connected to the second inverter 41 and then connected to the NOR gate 42, the second narrow pulse input terminal is connected to the NOR NOR gate 42, and the first narrow pulse input terminal is connected to the NOR NOR gate 42. The signals input from the narrow pulse input terminal and the second narrow pulse input terminal are integrated through the NOR gate 42 and then output a signal through the narrow pulse output terminal. The working principle is as follows Figure 4B shown.
[0060] like Figure 5As shown, the pulse shaper 12 adopts an 8th-order differential Butterworth low-pass filter structure with a cut-off frequency of 500MHz, including a differential port 1 and a differential port 2, and the differential port 1 is respectively connected to the ultra-wideband pulse generator. The output end of the DATA_P path and the output end of the DATA_N path in the 2 ; the differential port two is connected to the differential port of the balun one. The pulse shaper is used to transform a rectangular narrow pulse with a pulse width of about 2ns into a Gaussian bell pulse with a root time of about 2ns, obtain a differential signal of the Gaussian bell pulse, and then transmit it to the balun 1, and the Gaussian bell pulse is converted through the balun 1. The differential signal is converted into a single-ended signal. The Butterworth low-pass filter consists of two series branches, in which the inductors L1, L2, L3 and L4 form the first series branch, and the inductors L5, L6, L7 and L8 form the second series branch. On the two series branches, The inductance values ​​at the same position are equal, that is, L1 and L4 are equal, L2 and L5 are equal, L3 and L6 are equal, and L4 and L8 are equal. The inductance values ​​are L1=22nH, L2=27nH, L3=22nH, L4=6.8nH. Capacitors C1, C2, C3 and C4 are connected across two series branches, and the component values ​​are C1=1.3pF, C2=5pF, C3=6pF, C4=3.8pF respectively. The 3dB bandwidth of the filter is required to be 500MHz, and the ultra-wideband rectangular pulse is shaped into a Gaussian bell-shaped pulse by a pulse shaper.
[0061] like Image 6 As shown, the intermediate frequency amplifier 14 adopts a non-inverting input operational amplifier structure, the input end of the intermediate frequency amplifier is connected to the unbalanced port of the balun one; the output end of the intermediate frequency amplifier is connected to the single balun port of the second balun. The end ports are connected, and the balun two transforms into a differential signal with equal amplitude and phase difference of 180° and transmits it to the BPSK modulator through two output ports. The intermediate frequency amplifier 14 includes an operational amplifier 61, a feedback resistor R1 and a feedback resistor R2, the feedback resistor R1 and the feedback resistor R2 are in-phase input negative feedback voltage amplifier structures; the resistor R1 is 51Ω, R2 is 510Ω, and the voltage amplification factor is 10. The intermediate frequency amplifier 14 is used to amplify the single-channel differential Gaussian bell pulse signal output by the balun 13 and transmit it to the balun 2 15. The balun 2 is used to transform the amplified Gaussian bell pulse into equal amplitude and phase difference of 180°. The differential signal transformation of the balun one; the impedance of the balun one 13 and the balun two 15 are both 1:1.
[0062] like Figure 7 As shown, the BPSK modulator 18 includes a single-ended input differential output driver amplifier 71 and a double-balanced mixer, the double-balanced mixer 72 is connected to the balun 2 15, and the double-balanced mixer 72 includes two balanced ports, the IF port and the LO port. The BPSK modulator 18 is used to realize the BPSK modulation and up-conversion of the Gaussian bell pulse to form the UWB signal to be radiated with a specific center frequency; After being amplified by 10 times, it is converted into a differential signal at both ends by the balun II 15, and then connected to the IF+ port and IF- port of the double-balanced mixer 71; The center frequency of the radio frequency is linearly amplified by the small signal amplifier 17 to a power level of about 0dBm to 6dBm, and is connected to the LO port of the BPSK modulator 18. The LO signal generated by the PLL is driven by the single-ended input differential output in the BPSK modulator 18 The amplifier 71 is converted into two balanced signals of LO+ and LO-, which are connected to the LO+ and LO- balanced ports of the double-balanced mixer 72. The IF signal and the LO signal are up-converted by the mixer to realize frequency shift and form a BPSK modulated signal. UWB signal with a specific center frequency; the modulated UWB signal is radiated by the antenna after the power spectral density of the UWB signal is amplified to -41.3dBm/MHz by the variable gain amplifier 19 .
[0063] It should be understood that the parts not described in detail in this specification belong to the prior art. The above description of the preferred embodiment is relatively detailed, and therefore should not be considered as a limitation on the scope of protection of the patent of the present invention. Those of ordinary skill in the art, under the inspiration of the present invention, do not deviate from the scope of protection of the claims of the present invention. Below, alternatives or modifications can also be made, which all fall within the protection scope of the present invention, and the claimed protection scope of the present invention shall be subject to the appended claims.

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