Automated test apparatus for testing device under test comprising processing unit and program and/or data memory and automated test apparatus comprising test controller, one or more interfaces with device under test, shared memory and method for testing device under test

Abstract

One embodiment of the present invention is an automated testing apparatus (ATE) for testing a device under test (DUT) comprising a processing unit and a program and / or data store, where the processing unit is capable of executing code from the program and / or data store. The automated testing device is configured to establish communications, for example by uploading a program to the DUT using a first interface, such as a debug interface or a debug access port or a universal interface capable of accessing the processing unit for external control. A typical case of the first interface is a debug access to the DUT, which typically requires a limited data rate. In the case of the present invention, the first interface is an ATE access for test execution, such as an interface that allows access to a processing unit register. The first interface configures the DUT to turn on a second interface operating at a much higher data rate (higher than the first interface) for additional communications. Furthermore, the second interface may have an extended capability compared to the first interface, such as presenting its own memory as normal system memory to a processing unit of the DUT, only access time may be slower.

Description

technical field [0001] Embodiments according to the invention relate to automatic test equipment for testing a device under test comprising a processing unit and a memory. The memory may include program and / or data memory. [0002] A further embodiment according to the present invention relates to automatic test equipment comprising a test controller, one or more computer interfaces and shared memory. [0003] A further embodiment according to the invention relates to a method for testing a device under test (DUT). [0004] Embodiments of the invention relate generally to testing of digital semiconductor devices, and more particularly to system-type testing during device manufacture. [0005] A further embodiment according to the invention relates to a memory expansion method for system-on-chip testing. Background technique [0006] For production testing of digital semiconductor devices, structural testing methods are widely used. However, these tests focus on a complex...

AI Technical Summary

Problems solved by technology

This option has been published but rarely observed or applied due to its complexity

[0018] Using external memory modules on board, such as RAM, ROM, Flash ROM, etc., results in heavy usage of device pins, which can no longer be used for test access, thus causing structural test gaps

Furthermore, this option requires extensive maintenance and / or diagnostic work, such as verifying circuits, verifying and / or replacing program content

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