LDO circuit system without external output capacitor

Abstract

The invention discloses an LDO circuit system without an external output capacitor. The LDO circuit system is composed of two parallel loops. The first loop is composed of an input stage, a first buffer stage, a first power tube output stage, a first compensation network, a second compensation network, an output capacitor and an external load resistor, and the stability of the whole loop is jointly determined by the two loops under small output current; the second loop is composed of an input stage, a second buffer stage, a second power tube output stage, a first compensation network, a second compensation network, an output capacitor and an external load resistor, and the second loop determines the stability of the whole loop under medium current and large output current. The circuit of the first buffer stage is added, but the increased chip area is far smaller than the chip area occupied by reduction of the capacitance value of the compensation capacitor due to a traditional scheme measure; in addition, the low-capacitance compensation capacitor can also improve the slew rate, and the transient performance of the load is further improved.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to an LDO circuit system without an external output capacitor. Background technique [0002] The development of electronic technology requires the integration of more circuit modules to realize various functions in the SOC system. In order to avoid adverse effects on the operation of the circuit modules by using the same power supply voltage, an independent low dropout regulator (LDO) is generally used to supply power to each circuit module separately. This makes LDOs without external output capacitors the best choice for improving SOC system integration, reducing BOM costs, and reducing PCB area. [0003] Traditional LDO circuits without external output capacitors such as Figure 1A shown. NMOS transistors NM1A-NM4A and PMOS transistors PM1A-PM4A form an input stage with NM1A and NM2A as a differential pair. Current source I3A and current source I5A, PMOS transistor ...

AI Technical Summary

Problems solved by technology

In order to meet the demand of full load current, the sub-pole frequency P2A must be designed at a low frequency, so that the system can only obtain a small loop bandwidth under small load current, resulting in poor load transient response, large overcharge or output voltage low impact

To realize the main pole P1A with a lower frequency than the secondary pole, a compensation capacitor with a larger capacitance is required, which takes up more chip area; at the same time, the large-value capacitor causes a slower slew rate at the output of the input stage, further deteriorating load transient performance

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