Fast comparator circuit with wide common-mode input voltage

Abstract

The invention discloses a fast comparator circuit with a wide common-mode input voltage. The fast comparator circuit comprises a common-mode level control network, a first comparator, a second comparator, an output stage and a capacitance limiting circuit, the common-mode level control network converts the first differential signal into a second differential signal; the input end of the first comparator is connected with the output end of the common-mode level control network in the same direction; the input end of the second comparator is connected with the output end of the first comparator in the same direction; the input end of the output stage is connected with the output end of the second comparator in the same direction; the capacitance limiting circuit is connected with a first differential signal and is connected with the input end of the second comparator. According to the invention, very small offset voltage VOS and very high-speed dynamic signal transmission are respectively obtained in a manner of cascading two groups of comparators; therefore, mutual restriction between the offset voltage VOS and the signal transmission rate is avoided, the signal transmission rate is improved on the premise that the more accurate offset voltage VOS is guaranteed, and the signal quality is improved.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a fast comparator circuit with wide common-mode input voltage. Background technique [0002] Due to the characteristics of high data transmission rate, low noise and low signal crosstalk, differential input comparators are widely used in signal interface circuits, especially in signal receiver circuits. The receiver module receives the differential signal on the bus and converts the differential signal to a single-ended CMOS output signal at a conversion rate of several hundred megahertz. The signals on the bus usually have a wide common-mode voltage range, for example: the common-mode voltage range of LVDS (Low-Voltage Differential Signaling, low-voltage differential signal) signal is 0V to 2.4V, M-LVDS (Multipoint low Voltage Differential Signaling , multi-point low-voltage differential signal) The common-mode voltage range of the signal is -1V to 3.4V....

AI Technical Summary

Problems solved by technology

In order to obtain sufficient voltage gain and small input offset voltage, NMOS differential pairs and PMOS differential pairs need to be designed with large device sizes, but large-sized input devices will introduce non-negligible input capacitance

When performing serial or multipoint link signal transmission, the low-pass filter formed by this input capacitor will reduce the edge rate, thereby limiting the maximum transmission rate of the signal

And when the receiver is driven by a 50 ohm driver, the extra capacitive load brought by this input capacitor will cause extra jitter at the receiver input, which will affect the signal transmission quality

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