Silicon carbide accumulation state MOSFET with groove
A silicon carbide and silicon carbide substrate technology, applied in electrical components, circuits, semiconductor devices, etc., can solve problems such as low channel mobility and reduced on-resistance, and achieve high channel mobility and reduced on-resistance , The effect of reducing the channel resistance
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Embodiment 1
[0034] Such as figure 1 As shown, the silicon carbide accumulation MOSFET with trenches, taking the first conductivity type as N and the second conductivity type as P as an example, includes a silicon carbide substrate 101, wherein the doping concentration and type of the substrate are N+. A silicon carbide epitaxial layer 102 is grown on the silicon carbide substrate 101 , wherein the doping concentration and type of the epitaxial layer are N−. The back surface of the silicon carbide substrate 101 is covered with a drain metal electrode 111 to form a drain region of the MOSFET.
[0035] A groove is etched on the silicon carbide epitaxial layer 102, an oxide layer 107 is grown on the surface of the groove, and a gate polysilicon electrode 108 is arranged on the oxide layer 107 to form the gate region of the MOSFET to control the on and off of the device. The device can be turned on by applying a positive voltage to the polysilicon electrode 108 . A gate protection region 106...
Embodiment 2
[0039] Such as Figure 2-3 As shown, in this embodiment, on the basis of Embodiment 1, it is further defined that the accumulation layer 105 is arranged at intervals along the circumferential direction of the oxide layer 107; The accumulation layers 105 are distributed along the circumferential direction of the oxide layer 107 at intervals. Preferably, the distribution area in the circumferential direction of the oxide layer 107 is less than 50%. Under this solution, the thickness of the accumulation layer 105 can be slightly increased, reducing the difficulty of manufacturing process, and at the same time, the region can be completely depleted while reducing the channel resistance, and the channel can be kept closed when the gate is not turned on.
Embodiment 3
[0041] The difference between this embodiment and Embodiment 1 is that the first conductivity type is P, and the second conductivity type is N, that is, the silicon carbide substrate 101, the silicon carbide epitaxial layer 102, the source implantation region 104, and the accumulation layer 105 The conductivity type is P-type; the conductivity type of the blocking injection layer 103 and the withstand voltage injection region 112 is N-type; as a preferred method, the doping concentration and type of the silicon carbide substrate 101 are P+, and the silicon carbide epitaxial The doping concentration and type of the layer 102 are P-, the doping concentration and type of the source injection region 104 are P+, the doping concentration and type of the accumulation layer 105 are P-, and the doping concentration of the gate protection region 106 is The doping concentration and type of the blocking injection layer 103 are N+, and the doping concentration and type of the withstand ...
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